%A Jeffrey Markham
%T Applying semicustom CAD to full-custom design
%J VLSI Systems Design
%K vlsi_sdes
%V 6
%N 9
%D September 1985
%P 26-45

%Q VLSI Systems Design staff
%T Survey of IC layout CAD systems
%J VLSI Systems Design
%K vlsi_sdes
%V 6
%N 9
%D September 1985
%P 45-53

%A Rex A. Hoover
%A Raymond N. Winkel
%T A two-technology strategy
%J VLSI Systems Design
%K vlsi_sdes
%V 6
%N 9
%D September 1985
%P 54-61

%A Roderic Beresford
%T A profile of current applications of gate arrays and standard-cell ICs
%J VLSI Systems Design
%K vlsi_sdes
%V 6
%N 9
%D September 1985
%P 62-69

%A Alexandre Yakovlev
%T Designing self-timed systems
%J VLSI Systems Design
%K vlsi_sdes
%V 6
%N 9
%D September 1985
%P 70-93

%A James T. Healy
%T The marriage of CAE workstations and ATE
%J VLSI Systems Design
%K vlsi_sdes
%V 6
%N 9
%D September 1985
%P 94-105

%A Steve Perry
%A Sandor Kalman
%A Dave Pilling
%T Edge-based layout verification
%J VLSI Systems Design
%K vlsi_sdes
%V 6
%N 9
%D September 1985
%P 106-117

%A John Hennessy
%T VLSI RISC processors
%J VLSI Systems Design
%K vlsi_sdes
%V 6
%N 10
%D October 1985
%P 22-33

%A Eduardo B. Fernandez
%T Microprocessor architecture: the 32-bit generation
%J VLSI Systems Design
%K vlsi_sdes
%V 6
%N 10
%D October 1985
%P 34-47

%A Ernest L. Meyer
%T Application-specific hardware accelerators: an overview
%J VLSI Systems Design
%K vlsi_sdes
%V 6
%N 10
%D October 1985
%P 48-57

%A Bic Wood
%T The A-series accelerator: a case history
%J VLSI Systems Design
%K vlsi_sdes
%V 6
%N 10
%D October 1985
%P 58-61

%A Geoffrey Mott
%A Russell B. Hall
%T The utility of hardware accelerators in the design environment
%J VLSI Systems Design
%K vlsi_sdes
%V 6
%N 10
%D October 1985
%P 62-71

%A Bob Dahlberg
%T Hardware acceleration applied to gate array layout
%J VLSI Systems Design
%K vlsi_sdes
%V 6
%N 10
%D October 1985
%P 72-73

%A Hans Gethoeffer
%T Hardware acceleration for printed circuit board routing
%J VLSI Systems Design
%K vlsi_sdes
%V 6
%N 10
%D October 1985
%P 74-75

%A Steven Siegel
%A Michael E. Kaszynski
%T The design of alogic simulation accelerator
%J VLSI Systems Design
%K vlsi_sdes
%V 6
%N 10
%D October 1985
%P 76-84

%A Michael R. Butts
%T A general-purpose accelerator
%J VLSI Systems Design
%K vlsi_sdes
%V 6
%N 10
%D October 1985
%P 85-87

%Q VLSI Systems Design staff
%T Directory of automatic test equipment
%J VLSI Systems Design
%K vlsi_sdes
%V 6
%N 10
%D October 1985
%P 88-99

%A John M. Caraballo
%A John Silver
%T Current-mode logic technology for a radiation-hard VHSIC gate array
%J VLSI Systems Design
%K vlsi_sdes
%V 6
%N 11
%D November 1985
%P 20-29

%A Ernest L. Meyer
%T Survey of multiprocessors
%J VLSI Systems Design
%K vlsi_sdes
%V 6
%N 11
%D November 1985
%P 30-41

%A Stephen Evanczuk
%T Silicon compilers: no automatic route to acceptance
%J VLSI Systems Design
%K vlsi_sdes
%V 6
%N 11
%D November 1985
%P 42-47

%A Daniel D. Gajski
%T Silicon compilation
%J VLSI Systems Design
%K vlsi_sdes
%V 6
%N 11
%D November 1985
%P 48-65

%A John T. Nogatch
%A Tom Hedges
%T Automated design of CMOS leaf cells
%J VLSI Systems Design
%K vlsi_sdes
%V 6
%N 11
%D November 1985
%P 66-79

%A Gary G. De\ Palma
%T Architecture experimentation
%J VLSI Systems Design
%K vlsi_sdes
%V 6
%N 11
%D November 1985
%P 80-89

%A Gerald Fehr
%A Jon Long
%A Allan Tippets
%T A high-pin-count packaging scheme
%J VLSI Systems Design
%K vlsi_sdes
%V 6
%N 11
%D November 1985
%P 90-95

%A John A. Waocukauski
%A Edward B. Eichelberger
%A Donato O. Forlenza
%A Eric Lindbloom
%A Thomas McCarthy
%T Fault simulation for structured VLSI
%J VLSI Systems Design
%K vlsi_sdes
%V 6
%N 12
%D December 1985
%P 20-35

%A Kyushik Son
%T Fault simulation with the parallel value list algorithm
%J VLSI Systems Design
%K vlsi_sdes
%V 6
%N 12
%D December 1985
%P 36-45

%A Eric Archambeau
%T Testability analysis techniques: a critical survey
%J VLSI Systems Design
%K vlsi_sdes
%V 6
%N 12
%D December 1985
%P 46-53

%Q VLSI Systems Design staff
%T Survey of custom and semicustom ICs
%J VLSI Systems Design
%K vlsi_sdes
%V 6
%N 12
%D December 1985
%P 54-93

%A Jay Hiserote
%A James B. Morris
%A Robert D. Hunter
%T Semicustom IC simulation on CAE workstations
%J VLSI Systems Design
%K vlsi_sdes
%V 6
%N 12
%D December 1985
%P 94-110

%A Bruce Greer
%T Converting SPICE to vector code
%J VLSI Systems Design
%K vlsi_sdes
%V 7
%N 1
%D January 1986
%P 30-35

%A Shshriar Emami
%A Steve Brunner
%T Logic simulation on PCs
%J VLSI Systems Design
%K vlsi_sdes
%V 7
%N 1
%D January 1986
%P 36-39

%A Robert D. Hess
%A William C. Berg,\ Jr.
%T Performance of probabilistic fault grading
%J VLSI Systems Design
%K vlsi_sdes
%V 7
%N 1
%D January 1986
%P 40-47

%A Kunnau Chen
%T On-chip testability circuits for CMOS gate arrays
%J VLSI Systems Design
%K vlsi_sdes
%V 7
%N 1
%D January 1986
%P 48-53

%A B.J. Donlan
%A J.F. McDonald
%A R.H. Steinvorth
%A M.K. Dhodhi
%A G.F. Taylor
%A A.S. Bergendahl
%T The wafer transmission module
%J VLSI Systems Design
%K vlsi_sdes
%V 7
%N 1
%D January 1986
%P 54-59

%Q VLSI Systems Design staff
%T Survey of ASIC design centers
%J VLSI Systems Design
%K vlsi_sdes
%V 7
%N 1
%D January 1986
%P 60-97

%A Ernest L. Meyer
%T Gate array testability: a customer perspective
%J VLSI Systems Design
%K vlsi_sdes
%V 7
%N 6
%D June 1986
%P 34-45

%A Ron Lake
%T A fast 20K gate array with on-chip test system
%J VLSI Systems Design
%K vlsi_sdes
%V 7
%N 6
%D June 1986
%P 46-57

%A Evan Aurand
%T Architecture of a computer integrated engineering system
%J VLSI Systems Design
%K vlsi_sdes
%V 7
%N 6
%D June 1986
%P 58-69

%A Harold M. Rabbie
%A Robert W. Dahlberg
%A Herbert L. Hinstorff,\ Jr.
%T A workstation for cell-based IC layout
%J VLSI Systems Design
%K vlsi_sdes
%V 7
%N 6
%D June 1986
%P 70-84

%Q VLSI Systems Design staff
%T Survey of CAE systems
%J VLSI Systems Design
%K vlsi_sdes
%V 7
%N 6
%D June 1986
%P 85-107

%A Dean P. Johnson
%A Jim Lipman
%T IC packaging: an introduction for the VLSI designer
%J VLSI Systems Design
%K vlsi_sdes
%V 7
%N 6
%D June 1986
%P 108-124

%A Rochard Davis
%A Jerry Schappacher
%A Scott Gilstad
%T Board and microwave chip carriers for GaAs systems
%J VLSI Systems Design
%K vlsi_sdes
%V 7
%N 6
%D June 1986
%P 125-132

%A Pierre Irissou
%A Eugene Lee
%T An introduction to linear semicustom design
%J VLSI Systems Design
%K vlsi_sdes
%V 7
%N 7
%D July 1986
%P 24-31

%A Greg Barrow
%T A survey of circuit simulation programs
%J VLSI Systems Design
%K vlsi_sdes
%V 7
%N 7
%D July 1986
%P 32-45

%A Jeffrey T. Deutsch
%A Thomas D. Lovett
%A Michael Lee Squires
%T Parallel computing for VLSI circuit simulation
%J VLSI Systems Design
%K vlsi_sdes
%V 7
%N 7
%D July 1986
%P 46-55

%A Stephen Evanczuk
%T The desktop workstations: life, liberty and the pursuit of personal computers
%J VLSI Systems Design
%K vlsi_sdes
%V 7
%N 7
%D July 1986
%P 56-67

%A Ralph Marlett
%T Automated test generation of integrated circuits
%J VLSI Systems Design
%K vlsi_sdes
%V 7
%N 7
%D July 1986
%P 68-75

%A Chris Pieper
%T Stimulus data interchange format, part 1: test issues
%J VLSI Systems Design
%K vlsi_sdes
%V 7
%N 7
%D July 1986
%P 76-83

%A Renato N. Gadenz
%A W. Patrick Hays
%T A method for extensive verification of programmable VLSI devices
%J VLSI Systems Design
%K vlsi_sdes
%V 7
%N 7
%D July 1986
%P 84-91

%A William E. Den Beste
%T Tools for test development
%J VLSI Systems Design
%K vlsi_sdes
%V 7
%N 7
%D July 1986
%P 92-99

%A Stephen McNeary
%A Ratbin Putatunda
%A Howard Rifkin
%A Robert Robillard
%A David Smith
%T VITAL: a cell-based ASIC assembler
%J VLSI Systems Design
%K vlsi_sdes
%V 7
%N 11
%D November 1986
%P 22-33

%A Jiri Soukup
%T Place and route strategies
%J VLSI Systems Design
%K vlsi_sdes
%V 7
%N 11
%D November 1986
%P 34-45

%A Jonathan W. Greene
%T Layout-to-layout compaction for technology conversion
%J VLSI Systems Design
%K vlsi_sdes
%V 7
%N 11
%D November 1986
%P 46-53

%Q VLSI Systems Design Staff
%T Survey of gate arrays and cell libraries
%J VLSI Systems Design
%K vlsi_sdes
%V 7
%N 11
%D November 1986
%P 54-91

%A Sanfor Lebow
%T Multi-chip packaging
%J VLSI Systems Design
%K vlsi_sdes
%V 7
%N 11
%D November 1986
%P 92-95

%A Gary Beihl
%A Shekhar Borkar
%T A behavioral simulation shell
%J VLSI Systems Design
%K vlsi_sdes
%V 7
%N 11
%D November 1986
%P 96-101

%A Ralph Haines
%A Chris Phillips
%T Semicustom design with a microcontroller core
%J VLSI Systems Design
%K vlsi_sdes
%V 7
%N 12
%D December 1986
%P 26-31

%Q VLSI Systems Design Staff
%T Guide to core processors
%J VLSI Systems Design
%K vlsi_sdes
%V 7
%N 12
%D December 1986
%P 32-41

%A Bruce Erickson
%T Automation and simulation in large system design
%J VLSI Systems Design
%K vlsi_sdes
%V 7
%N 12
%D December 1986
%P 42-49

%A Laung-Terng Wang
%A Edward J. McCluskey
%T Feedback shift registers for self-testing circuits
%J VLSI Systems Design
%K vlsi_sdes
%V 7
%N 12
%D December 1986
%P 50-61

%A J.F. McDonald
%A B.J. Donlan
%A R.H. Steinvorth
%A H. Greub
%A M. Dhodhi
%A J.S. Kim
%A A.S. Bergendahl
%T Yield of wafer-scale interconnections
%J VLSI Systems Design
%K vlsi_sdes
%V 7
%N 12
%D December 1986
%P 62-67

%A Kwaku Mensa
%T The VLSI-to-substrate connection
%J VLSI Systems Design
%K vlsi_sdes
%V 7
%N 12
%D December 1986
%P 68-73

%A Mark Mayotte
%T An engineering design management system
%J VLSI Systems Design
%K vlsi_sdes
%V 8
%N 1
%D January 1987
%P 30-398

%A Biowa Banerjee
%T Handling the power dissipation of ECL gate arrays
%J VLSI Systems Design
%K vlsi_sdes
%V 8
%N 1
%D January 1987
%P 40-49

%A F.P.M. Beenker
%T Systematic and structured methods for digital board testing
%J VLSI Systems Design
%K vlsi_sdes
%V 8
%N 1
%D January 1987
%P 50-59

%Q VLSI Systems Design Staff
%T Directory of ASIC design centers
%J VLSI Systems Design
%K vlsi_sdes
%V 8
%N 1
%D January 1987
%P 60-87

%A James A. Schoeffel
%A Michael L. Rieger
%T Economics of fast-turn wafer production
%J VLSI Systems Design
%K vlsi_sdes
%V 8
%N 2
%D February 1987
%P 22-35

%A Michael D. McClure
%T PLD breadboarding of gate array designs
%J VLSI Systems Design
%K vlsi_sdes
%V 8
%N 2
%D February 1987
%P 36-43

%A Shing-Kong
%A David Wood
%A Garth Gibson
%A Randy Katz
%A David Patterson
%T Design methodology for a VLSI multiprocessor workstation
%J VLSI Systems Design
%K vlsi_sdes
%V 8
%N 2
%D February 1987
%P 44-55
%K SPUR

%A William D. Billowitch
%T Board-level simulation using models with X-state handling
%J VLSI Systems Design
%K vlsi_sdes
%V 8
%N 2
%D February 1987
%P 56-61

%A Stephen Evanczuk
%T Mixed-level simulation acceleration
%J VLSI Systems Design
%K vlsi_sdes
%V 8
%N 2
%D February 1987
%P 62-69

%Q VLSI Systems Design Staff
%T 1987 survey of logic simulators
%J VLSI Systems Design
%K vlsi_sdes
%V 8
%N 2
%D February 1987
%P 70-87

%A Kirk Holden
%A David Mothersole
%A Raju Vegesna
%T Memory management in the 68030 microprocessor
%J VLSI Systems Design
%K vlsi_sdes
%V 8
%N 2
%D February 1987
%P 88-104