%A D.M. Chapiro %T Globally-asynchronous locally-synchronous systems %R Ph.D. thesis %I Stanford University %C Stanford, California %D October 1984 %A F.C. Chow %T A portable machine-independent global optimizer - design and measurements %R Ph.D. dissertation %I Stanford University %C Stanford, California %D December 1983 %A Y.K. Dalal %T Broadcast protocols in packet-switched computer networks %R Ph.D. dissertation %I Stanford University %C Stanford, California %D 1977 %A M. Horowitz %T Timing models for MOS circuits %R Ph.D. thesis %I Stanford University %C Stanford, California %D December 1983 %A T.P. Mann %T A decentralized naming facility %R Ph.D. thesis %I Stanford University %C Stanford, California %D 1986 %A David Cooke Noice %T A clocking discipline for two-phase digital integrated circuits %R Ph.D. thesis %I Stanford University %C Stanford, California %D January 1983 %O University Microfilms 8314482 %A D. Sleator %T An (nm log n) algorithm for maximal network flow %R Ph.D. thesis %I Stanford University %C Stanford, California %D November 1980 %A D.E. Smith %T Controlling inference %R Ph.D. thesis %I Stanford University %C Stanford, California %D July 1985 %A R.J. Treitel %T Sequentialising logic programs %R Ph.D. thesis %I Stanford University %C Stanford, California %D 1986 %A Evan Tick %T Studies in Prolog Architectures %R Ph.D. thesis %I Stanford University %C Stanford, California %D 1987 %X ABSTRACT: This dissertation addresses the problem of how logic programs can be made to execute at high speeds. Prolog, chosen as a representative logic programming language, differs from procedural languages in that it is applicative, nondeterminate and uses pattern matching as its primary operation. Program performance is directly related to memory performance because high speed processors are ultimately limited by memory bandwidth and architectures that require less bandwidth have greater potential for high performance. A derivation of a family of canonical Prolog architectures is given from the first principles of ideal machine architectures. The Warren Abstract Machine (WAM) architecture is shown to be a member of this family. Measurements of the Prolog Canonical Interpretive Form indicate upper memory-performance bounds afforded by ideal attributes. Analysis of high-level architecture statistics indicate the cost of attributes such as nondeterminacy and point to efficient memory designs. High speed uniprocessor performance is necessary, even within a multiprocessor, because not all types of parallelism exist or can be exploited in all applications. Within a shared memory multiprocessor, local processor memories are necessary to reduce bandwidth and allow undegraded execution of sequential code. Two-level hierarchies for both sequential and parallel Prolog architectures are modeled. Local memories are measured with trace driven simulations. Main memories are measured with queueing models. For sequential Prolog, various hierarchies are analyzed with the WAM architecture. For parallel Prolog, various shared memory multiprocessors are analyzed with the Restricted AND-Parallelism (RAP) architecture of Hermenegildo. Local memory consistency protocols for RAP are designed and measured. %A Jeffrey Scott Vitter %T Analysis of coalesced hashing %R Ph.D. thesis %I Stanford University %C Stanford, California %D August 1980 %A J.E. Vuillemin %T Proof techniques for recursive programs %R Ph.D. thesis %I Stanford University %C Stanford, California %D 1973 %A T. Wagner %T Hardware verification %R Ph.D. thesis %I Stanford University %C Stanford, California %D September 1977 %A W. Zwaenepoel %T Message passing on local network %R Ph.D. thesis %I Stanford University %C Stanford, California %D October 1984