%A I. Koren
%T A reconfigurable and fault-tolerant VLSI multiprocessor array
%R TR 81-1
%I Department of Computer Science,
University of Southern California
%C Los Angeles
%D 1981

%A I. Koren
%T On area & yield considerations for systems
%R TR 82-5
%I Department of Computer Science,
University of Southern California
%C Los Angeles
%D 1982

%A C. Breuer
%T A placement algorithm for array processors
%R TR 82-7
%I Department of Computer Science,
University of Southern California
%C Los Angeles
%D 1982

%A F. Cohen
%T The USC roving emulator
%R TR 82-7
%I Department of Computer Science,
University of Southern California
%C Los Angeles
%D 1982

%A G. Parker
%T The effect of register-transfer design tradeoffs
on chip area and performance
%R TR 82-8
%I Department of Computer Science,
University of Southern California
%C Los Angeles
%D 1982

%A B.C. Ismaeel
%T Roving emulation as applied to a (255.223) RS-encoder system
%R TR 83-1
%I Department of Computer Science,
University of Southern California
%C Los Angeles
%D 1983

%A A. Parker
%A N. Park
%A D.W. Knapp
%T Simulation effectiveness design verification
%R TR 84-2
%I Department of Computer Science,
University of Southern California
%C Los Angeles
%D 1984

%A J. Bannur
%A A. Varma
%T The VLSI implementation of a square root algorithm
%R TR 84-3
%I Department of Computer Science,
University of Southern California
%C Los Angeles
%D 1984

%A N. Park
%A A. Parker
%T Synthesis of optimal pipeline clocking schemes
%R TR 85-1
%I Department of Computer Science,
University of Southern California
%C Los Angeles
%D 1985