%A Dileep P. Bhandarkar
%A Samuel H. Fuller
%T Markov chain models for analyzing memory interference
in multiprocessor computer systems
%J Proceedings of the First Annual Symposium on Computer Architecture
%E G.J. Lipovski
%E S.A. Szygenda
%D December 1973
%O published as SIGARCH Computer Architecture News 2:4
%K isca isca1
%P 1-10

%A George A. Anderson
%T Interconnecting a distributed processor system for avionics
%J Proceedings of the First Annual Symposium on Computer Architecture
%E G.J. Lipovski
%E S.A. Szygenda
%D December 1973
%O published as SIGARCH Computer Architecture News 2:4
%K isca isca1
%P 11-20

%A Rodney Goke
%A G.J. Lipovski
%T Banyan networks for partitioning multiprocessor systems
%J Proceedings of the First Annual Symposium on Computer Architecture
%E G.J. Lipovski
%E S.A. Szygenda
%D December 1973
%O published as SIGARCH Computer Architecture News 2:4
%K isca isca1
%P 21-30

%A Harry F. Jordan
%A Burton J. Smith
%T Structure of digital system description languages
%J Proceedings of the First Annual Symposium on Computer Architecture
%E G.J. Lipovski
%E S.A. Szygenda
%D December 1973
%O published as SIGARCH Computer Architecture News 2:4
%K isca isca1
%P 31-40

%A John A.N. Lee
%T VDL - a definitional system for all levels
%J Proceedings of the First Annual Symposium on Computer Architecture
%E G.J. Lipovski
%E S.A. Szygenda
%D December 1973
%O published as SIGARCH Computer Architecture News 2:4
%K isca isca1
%P 41-50

%A Charles H. Radoy
%A George P. Copeland,\ Jr.
%A G.J. Lipovski
%T A methodology for parallel processing design tradeoffs
%J Proceedings of the First Annual Symposium on Computer Architecture
%E G.J. Lipovski
%E S.A. Szygenda
%D December 1973
%O published as SIGARCH Computer Architecture News 2:4
%K isca isca1
%P 51-60

%A S.F. Reddaway
%T DAP - a distributed array processor
%J Proceedings of the First Annual Symposium on Computer Architecture
%E G.J. Lipovski
%E S.A. Szygenda
%D December 1973
%O published as SIGARCH Computer Architecture News 2:4
%K isca isca1
%P 61-70

%A Peter M. Kogge
%T Maximal rate pipelined solutions to recurrence problems
%J Proceedings of the First Annual Symposium on Computer Architecture
%E G.J. Lipovski
%E S.A. Szygenda
%D December 1973
%O published as SIGARCH Computer Architecture News 2:4
%K isca isca1
%P 71-80

%A Tilak Agerwala
%A Mike Flynn
%T Comments on capabilities, limitations and 'correctness' of Petri nets
%J Proceedings of the First Annual Symposium on Computer Architecture
%E G.J. Lipovski
%E S.A. Szygenda
%D December 1973
%O published as SIGARCH Computer Architecture News 2:4
%K isca isca1
%P 81-90

%A Wayne E. Omohundro
%A James H. Tracey
%T Flowware - a flow charting procedure to describe digital networks
%J Proceedings of the First Annual Symposium on Computer Architecture
%E G.J. Lipovski
%E S.A. Szygenda
%D December 1973
%O published as SIGARCH Computer Architecture News 2:4
%K isca isca1
%P 91-100

%A M.R. Barbacci
%A D.P. Siewiorek
%T Automated exploration of the design space for register transfer (RT) systems
%J Proceedings of the First Annual Symposium on Computer Architecture
%E G.J. Lipovski
%E S.A. Szygenda
%D December 1973
%O published as SIGARCH Computer Architecture News 2:4
%K isca isca1
%P 101-110

%A T.A. Laliotis
%T Implementation aspects of the Symbol hardware compiler
%J Proceedings of the First Annual Symposium on Computer Architecture
%E G.J. Lipovski
%E S.A. Szygenda
%D December 1973
%O published as SIGARCH Computer Architecture News 2:4
%K isca isca1
%P 111-120

%A George P. Copeland,\ Jr.
%A G.J. Lipovski
%A Stanley Y.W. Su
%T The architecture of CASSM: a cellular system for non-numeric processing
%J Proceedings of the First Annual Symposium on Computer Architecture
%E G.J. Lipovski
%E S.A. Szygenda
%D December 1973
%O published as SIGARCH Computer Architecture News 2:4
%K isca isca1
%P 121-130

%A John M. Hemphill
%A S.A. Szygenda
%T Deriving design guidelines for diagnosable computer systems
%J Proceedings of the First Annual Symposium on Computer Architecture
%E G.J. Lipovski
%E S.A. Szygenda
%D December 1973
%O published as SIGARCH Computer Architecture News 2:4
%K isca isca1
%P 131-140

%A Behrooz Parhami
%A Algirdas Avizienis
%T Design of fault-tolerant associative processors
%J Proceedings of the First Annual Symposium on Computer Architecture
%E G.J. Lipovski
%E S.A. Szygenda
%D December 1973
%O published as SIGARCH Computer Architecture News 2:4
%K isca isca1
%P 141-150

%A M.A. Fischler
%A D. Firschein
%T A fault tolerant multiprocessor architecture
for real time control applications
%J Proceedings of the First Annual Symposium on Computer Architecture
%E G.J. Lipovski
%E S.A. Szygenda
%D December 1973
%O published as SIGARCH Computer Architecture News 2:4
%K isca isca1
%P 151-160

%A G.J. Lipovski
%T A varistructured fail-soft cellular computer
%J Proceedings of the First Annual Symposium on Computer Architecture
%E G.J. Lipovski
%E S.A. Szygenda
%D December 1973
%O published as SIGARCH Computer Architecture News 2:4
%K isca isca1
%P 161-170

%A Jean Caucher
%A Christian Rey
%T A hardware laboratory for computer architecture research
%J Proceedings of the First Annual Symposium on Computer Architecture
%E G.J. Lipovski
%E S.A. Szygenda
%D December 1973
%O published as SIGARCH Computer Architecture News 2:4
%K isca isca1
%P 171-180

%A P.J. Knoke
%T Simulation exercises for computer architecture education
%J Proceedings of the First Annual Symposium on Computer Architecture
%E G.J. Lipovski
%E S.A. Szygenda
%D December 1973
%O published as SIGARCH Computer Architecture News 2:4
%K isca isca1
%P 181-190

%A M.E. Sloan
%T Computer architecture courses in electrical engineering departments
%J Proceedings of the First Annual Symposium on Computer Architecture
%E G.J. Lipovski
%E S.A. Szygenda
%D December 1973
%O published as SIGARCH Computer Architecture News 2:4
%K isca isca1
%P 191-200

%A B. Hartenstein
%T Increasing hardware complexity -
a challenge to computer architecture education
%J Proceedings of the First Annual Symposium on Computer Architecture
%E G.J. Lipovski
%E S.A. Szygenda
%D December 1973
%O published as SIGARCH Computer Architecture News 2:4
%K isca isca1
%P 201-210

%A George Rossmann
%T Review of the workshop on computer architecture education
%J Proceedings of the First Annual Symposium on Computer Architecture
%E G.J. Lipovski
%E S.A. Szygenda
%D December 1973
%O published as SIGARCH Computer Architecture News 2:4
%K isca isca1
%P 211-220

%A Richard G. Cooper
%T Micromodules: microprogrammable building blocks for hardware development
%J Proceedings of the First Annual Symposium on Computer Architecture
%E G.J. Lipovski
%E S.A. Szygenda
%D December 1973
%O published as SIGARCH Computer Architecture News 2:4
%K isca isca1
%P 221-230

%A S.H. Fuller
%A D.P. Siewiorek
%A R.J. Swan
%T Computer modules: an architecture for large digital modules
%J Proceedings of the First Annual Symposium on Computer Architecture
%E G.J. Lipovski
%E S.A. Szygenda
%D December 1973
%O published as SIGARCH Computer Architecture News 2:4
%K isca isca1
%P 231-240

%A Rodney Zaks
%T A microprogrammed architecture for front end processing
%J Proceedings of the First Annual Symposium on Computer Architecture
%E G.J. Lipovski
%E S.A. Szygenda
%D December 1973
%O published as SIGARCH Computer Architecture News 2:4
%K isca isca1
%P 241-250

%A Z.G. Vranesic
%A V.C. Hamacher
%A Y.Y. Leung
%T Design of a fully variable-length structured minicomputer
%J Proceedings of the First Annual Symposium on Computer Architecture
%E G.J. Lipovski
%E S.A. Szygenda
%D December 1973
%O published as SIGARCH Computer Architecture News 2:4
%K isca isca1
%P 251-260

%A Orin E. Marvel
%T HAPPE Honeywell associative parallel processing ensemble
%J Proceedings of the First Annual Symposium on Computer Architecture
%E G.J. Lipovski
%E S.A. Szygenda
%D December 1973
%O published as SIGARCH Computer Architecture News 2:4
%K isca isca1
%P 261-270

%A Mario R. Schaffner
%T A computer architecture and its programming language
%J Proceedings of the First Annual Symposium on Computer Architecture
%E G.J. Lipovski
%E S.A. Szygenda
%D December 1973
%O published as SIGARCH Computer Architecture News 2:4
%K isca isca1
%P 271-280

%A Gordon Bell
%A William S. Strecker
%T Computer structures: what have we learned from the PDP-11 ?
%J Proceedings of the Third Annual International Symposium on Computer Architecture
%D January 1976
%O published as SIGARCH Computer Architecture News 4:4
%K isca isca3
%P 1-14

%A Helmut Kerner
%A Werner Beyerle
%T A PMS level language for performance evaluation modelling (V-PMS)
%J Proceedings of the Third Annual International Symposium on Computer Architecture
%D January 1976
%O published as SIGARCH Computer Architecture News 4:4
%K isca isca3
%P 15-19

%A M. Moalla
%A C. Saucier
%A J. Sifakis
%A M. Zachariades
%T A design tool for the multilevel description and simulation
of systems of interconnected modules
%J Proceedings of the Third Annual International Symposium on Computer Architecture
%D January 1976
%O published as SIGARCH Computer Architecture News 4:4
%K isca isca3
%P 20-27

%A Jonathan Allen
%T A course in computer structures
%J Proceedings of the Third Annual International Symposium on Computer Architecture
%D January 1976
%O published as SIGARCH Computer Architecture News 4:4
%K isca isca3
%P 28-32

%A George E. Rossmann
%T The IEEE Computer Society task force on computer architecture
%J Proceedings of the Third Annual International Symposium on Computer Architecture
%D January 1976
%O published as SIGARCH Computer Architecture News 4:4
%K isca isca3
%P 33

%A Lawrence C. Widdoes
%T The Minerva multi-microprocessor
%J Proceedings of the Third Annual International Symposium on Computer Architecture
%D January 1976
%O published as SIGARCH Computer Architecture News 4:4
%K isca isca3
%P 34-39

%A R.G. Arnold
%A E.W. Page
%T A hierarchical restructurable multi-microprocessor architecture
%J Proceedings of the Third Annual International Symposium on Computer Architecture
%D January 1976
%O published as SIGARCH Computer Architecture News 4:4
%K isca isca3
%P 40-45

%A Robert McGill
%A John Steinhoff
%T A multimicroprocessor approach to numerical analysis:
an application to gaming problems
%J Proceedings of the Third Annual International Symposium on Computer Architecture
%D January 1976
%O published as SIGARCH Computer Architecture News 4:4
%K isca isca3
%P 46-51

%A John E. Jensen
%A Jean-Loup Baer
%T A model of interference in a shared resource multiprocessor
%J Proceedings of the Third Annual International Symposium on Computer Architecture
%D January 1976
%O published as SIGARCH Computer Architecture News 4:4
%K isca isca3
%P 52-57

%A C. Leung
%A D. Misunas
%A A. Neczwid
%A J. Dennis
%T A computer simulation facility for packet communication architecture
%J Proceedings of the Third Annual International Symposium on Computer Architecture
%D January 1976
%O published as SIGARCH Computer Architecture News 4:4
%K isca isca3
%P 58-63

%A S.L. Rege
%T Cost, performance and size tradeoffs
for different levels in a memory hierarchy
%J Proceedings of the Third Annual International Symposium on Computer Architecture
%D January 1976
%O published as SIGARCH Computer Architecture News 4:4
%K isca isca3
%P 64-67

%A Paul E. Dworak
%A Alice C. Parker
%T An input interface for a real-time digital sound generation system
%J Proceedings of the Third Annual International Symposium on Computer Architecture
%D January 1976
%O published as SIGARCH Computer Architecture News 4:4
%K isca isca3
%P 68-73

%A Michael C. Mulder
%A Patrick P. Fasang
%T A microprocessor oriented data acquisition and control system
for power control
%J Proceedings of the Third Annual International Symposium on Computer Architecture
%D January 1976
%O published as SIGARCH Computer Architecture News 4:4
%K isca isca3
%P 74-78

%A H.M. Gladney
%A G. Hochweller
%T Multiprogramming for real-time applications
%J Proceedings of the Third Annual International Symposium on Computer Architecture
%D January 1976
%O published as SIGARCH Computer Architecture News 4:4
%K isca isca3
%P 79-85

%A Theodore H. Kehl
%T Basil architecture - an HLL minicomputer
%J Proceedings of the Third Annual International Symposium on Computer Architecture
%D January 1976
%O published as SIGARCH Computer Architecture News 4:4
%K isca isca3
%P 86-92

%A Harold W. Lawson,\ Jr.
%T Function distribution in computer system architectures
%J Proceedings of the Third Annual International Symposium on Computer Architecture
%D January 1976
%O published as SIGARCH Computer Architecture News 4:4
%K isca isca3
%P 93-97

%A Chris A. Vissers
%T Interface, a dispersed architecture
%J Proceedings of the Third Annual International Symposium on Computer Architecture
%D January 1976
%O published as SIGARCH Computer Architecture News 4:4
%K isca isca3
%P 98-104

%A A. Thomasian
%A A. Avizienis
%T A design study of a shared resource computing system
%J Proceedings of the Third Annual International Symposium on Computer Architecture
%D January 1976
%O published as SIGARCH Computer Architecture News 4:4
%K isca isca3
%P 105-112

%A W.S. Ford
%A V.C. Hamacher
%T Hardware support for inter-process communication and processor sharing
%J Proceedings of the Third Annual International Symposium on Computer Architecture
%D January 1976
%O published as SIGARCH Computer Architecture News 4:4
%K isca isca3
%P 113-118

%A Cecil C. Reames
%A Ming T. Liu
%T Design and simulation of the Distributed Loop Computer Network (DLCN)
%J Proceedings of the Third Annual International Symposium on Computer Architecture
%D January 1976
%O published as SIGARCH Computer Architecture News 4:4
%K isca isca3
%P 124-129

%A Paolo Franchi
%T Distribution of functions and control in RPCNET
%J Proceedings of the Third Annual International Symposium on Computer Architecture
%D January 1976
%O published as SIGARCH Computer Architecture News 4:4
%K isca isca3
%P 130-135

%A Laddy D. Wittie
%T Efficient message routing in mega-micro-computer networks
%J Proceedings of the Third Annual International Symposium on Computer Architecture
%D January 1976
%O published as SIGARCH Computer Architecture News 4:4
%K isca isca3
%P 136-140

%A Terry A. Welch
%T An investigation of descriptor oriented architectures
%J Proceedings of the Third Annual International Symposium on Computer Architecture
%D January 1976
%O published as SIGARCH Computer Architecture News 4:4
%K isca isca3
%P 141-146

%A E.A. Feustel
%T Tagged architecture and the semantics of programming languages:
extensible types
%J Proceedings of the Third Annual International Symposium on Computer Architecture
%D January 1976
%O published as SIGARCH Computer Architecture News 4:4
%K isca isca3
%P 147-150

%A A.P. Batson
%A R.E. Brundage
%A J.P. Kearns
%T Design data for Algol-60 machines
%J Proceedings of the Third Annual International Symposium on Computer Architecture
%D January 1976
%O published as SIGARCH Computer Architecture News 4:4
%K isca isca3
%P 151-154

%A William D. Strecker
%T Cache memories for PDP-11 family computers
%J Proceedings of the Third Annual International Symposium on Computer Architecture
%D January 1976
%O published as SIGARCH Computer Architecture News 4:4
%K isca isca3
%P 155-158

%A Janak H. Patel
%A Edward S. Davidson
%T Improving the throughput of a pipeline by insertion of delays
%J Proceedings of the Third Annual International Symposium on Computer Architecture
%D January 1976
%O published as SIGARCH Computer Architecture News 4:4
%K isca isca3
%P 159-164

%A A.M. Abd-Alla
%A Laird H. Moffett
%T On-line architecture tuning using microcapture
%J Proceedings of the Third Annual International Symposium on Computer Architecture
%D January 1976
%O published as SIGARCH Computer Architecture News 4:4
%K isca isca3
%P 165-171

%A Leonard D. Healy
%T A character-oriented context-addressed segment-sequential storage
%J Proceedings of the Third Annual International Symposium on Computer Architecture
%D January 1976
%O published as SIGARCH Computer Architecture News 4:4
%K isca isca3
%P 172-177

%A J.A. Bush
%A G.J. Lipovski
%A S.Y.W. Su
%A J.K. Watson
%A S.J. Ackerman
%T Some implementations of segment sequential functions
%J Proceedings of the Third Annual International Symposium on Computer Architecture
%D January 1976
%O published as SIGARCH Computer Architecture News 4:4
%K isca isca3
%P 178-185

%A M. Demartinis
%A G.J. Lipovski
%A S.Y.W. Su
%A J.K. Watson
%T A self managing secondary memory system
%J Proceedings of the Third Annual International Symposium on Computer Architecture
%D January 1976
%O published as SIGARCH Computer Architecture News 4:4
%K isca isca3
%P 186-194

%A Samuel H. Fuller
%T Price/performance comparison of C.mmp and the PDP-10
%J Proceedings of the Third Annual International Symposium on Computer Architecture
%D January 1976
%O published as SIGARCH Computer Architecture News 4:4
%K isca isca3
%P 195-204

%A Yaohan Chu
%T Architecture of a hardware data interpreter
%J Proceedings of the Fourth Annual International Symposium on Computer Architecture
%D March 1977
%O published as SIGARCH Computer Architecture News 5:7
%K isca isca4
%P 1-9

%A Subrata Dasgupta
%T The design of some language constructs for horizontal microprogramming
%J Proceedings of the Fourth Annual International Symposium on Computer Architecture
%D March 1977
%O published as SIGARCH Computer Architecture News 5:7
%K isca isca4
%P 10-16

%A E. Douglas Jensen
%A Richard Y. Kain
%T The Honeywell modular microprogram machine: M^3
%J Proceedings of the Fourth Annual International Symposium on Computer Architecture
%D March 1977
%O published as SIGARCH Computer Architecture News 5:7
%K isca isca4
%P 17-28

%A Richard R. Ramseyer
%A Andries van\ Dam
%T A multi-microprocessor implementation of a general purpose pipelined CPU
%J Proceedings of the Fourth Annual International Symposium on Computer Architecture
%D March 1977
%O published as SIGARCH Computer Architecture News 5:7
%K isca isca4
%P 29-34

%A C.V. Ravi
%A Torben Moller
%T A hierarchical microcomputer system for hardware and software development
%J Proceedings of the Fourth Annual International Symposium on Computer Architecture
%D March 1977
%O published as SIGARCH Computer Architecture News 5:7
%K isca isca4
%P 35-40

%A J. Archer Harris
%A David R. SMith
%T Hierarchical multiprocessor organizations
%J Proceedings of the Fourth Annual International Symposium on Computer Architecture
%D March 1977
%O published as SIGARCH Computer Architecture News 5:7
%K isca isca4
%P 41-48

%A K. Murakami
%A S. Mishikawa
%A M. Sato
%T Poly-processor system analysis and design
%J Proceedings of the Fourth Annual International Symposium on Computer Architecture
%D March 1977
%O published as SIGARCH Computer Architecture News 5:7
%K isca isca4
%P 49-56

%A Guy Mazare
%T A few examples of how to use a symmetrical multi-micro-processor
%J Proceedings of the Fourth Annual International Symposium on Computer Architecture
%D March 1977
%O published as SIGARCH Computer Architecture News 5:7
%K isca isca4
%P 57-62

%A Peter M. Kogge
%T The microprogramming of pipelined processors
%J Proceedings of the Fourth Annual International Symposium on Computer Architecture
%D March 1977
%O published as SIGARCH Computer Architecture News 5:7
%K isca isca4
%P 63-69

%A Howard Jay Siegel
%T The microprogramming of various types
of SIMD machine interconnection networks
%J Proceedings of the Fourth Annual International Symposium on Computer Architecture
%D March 1977
%O published as SIGARCH Computer Architecture News 5:7
%K isca isca4
%P 70-79

%A B. Ramakrishna Rau
%A George E. Rossmann
%T The effect of instruction fetch strategies
upon the performance of pipelined instruction units
%J Proceedings of the Fourth Annual International Symposium on Computer Architecture
%D March 1977
%O published as SIGARCH Computer Architecture News 5:7
%K isca isca4
%P 80-89

%A S.R. Ahuja
%A J.R. Jump
%T A modular memory scheme for array processing
%J Proceedings of the Fourth Annual International Symposium on Computer Architecture
%D March 1977
%O published as SIGARCH Computer Architecture News 5:7
%K isca isca4
%P 90-94

%A Leonard S. Haynes
%T The architecture of an Algol 60 computer
implemented with distributed processors
%J Proceedings of the Fourth Annual International Symposium on Computer Architecture
%D March 1977
%O published as SIGARCH Computer Architecture News 5:7
%K isca isca4
%P 95-104

%A Herbert Sullivan
%A Theodore R. Bashkow
%T A large scale, homogenous, fully distributed parallel machine. I
%J Proceedings of the Fourth Annual International Symposium on Computer Architecture
%D March 1977
%O published as SIGARCH Computer Architecture News 5:7
%K isca isca4
%P 105-117

%A Herbert Sullivan
%A Theodore R. Bashkow
%A David Klappholz
%T A large scale, homogenous, fully distributed parallel machine. II
%J Proceedings of the Fourth Annual International Symposium on Computer Architecture
%D March 1977
%O published as SIGARCH Computer Architecture News 5:7
%K isca isca4
%P 118-124

%A G. Jack Lipovski
%T On virtual memories and micronetworks
%J Proceedings of the Fourth Annual International Symposium on Computer Architecture
%D March 1977
%O published as SIGARCH Computer Architecture News 5:7
%K isca isca4
%P 125-134

%A Jon C. Strauss
%T Considerations for new tactical computer systems
%J Proceedings of the Fourth Annual International Symposium on Computer Architecture
%D March 1977
%O published as SIGARCH Computer Architecture News 5:7
%K isca isca4
%P 135-140

%A Kenneth J. Thurber
%A Peter C. Patton
%A Robert C. Deward
%A Jon C. Strauss
%A Thomas W. Petschauer
%T An advanced tactical computer concept
%J Proceedings of the Fourth Annual International Symposium on Computer Architecture
%D March 1977
%O published as SIGARCH Computer Architecture News 5:7
%K isca isca4
%P 141-146

%A Gary J. Nutt
%T Microprocessor implementation of a parallel processor
%J Proceedings of the Fourth Annual International Symposium on Computer Architecture
%D March 1977
%O published as SIGARCH Computer Architecture News 5:7
%K isca isca4
%P 147-152

%A Paul Dworak
%A Alice C. Parker
%A Richard Blum
%T The design and implementation of a real-time sound generation system
%J Proceedings of the Fourth Annual International Symposium on Computer Architecture
%D March 1977
%O published as SIGARCH Computer Architecture News 5:7
%K isca isca4
%P 153-158

%A A.C. Parker
%A A.H. Nagle
%T Hardware/software tradeoffs
in a variable word width, variable queue length buffer memory
%J Proceedings of the Fourth Annual International Symposium on Computer Architecture
%D March 1977
%O published as SIGARCH Computer Architecture News 5:7
%K isca isca4
%P 159-164

%A Bernard L. Peuto
%A Leonard J. Shustek
%T An instruction timing model of CPU performance
%J Proceedings of the Fourth Annual International Symposium on Computer Architecture
%D March 1977
%O published as SIGARCH Computer Architecture News 5:7
%K isca isca4
%P 165-178

%A Cornelis H. Hoogendoorn
%T Reduction of memory interference in multiprocessor systems
%J Proceedings of the Fourth Annual International Symposium on Computer Architecture
%D March 1977
%O published as SIGARCH Computer Architecture News 5:7
%K isca isca4
%P 179-183

%A D.W. Hammerstrom
%A E.S. Davidson
%T Information content of CPU memory referencing behavior
%J Proceedings of the Fourth Annual International Symposium on Computer Architecture
%D March 1977
%O published as SIGARCH Computer Architecture News 5:7
%K isca isca4
%P 184-192

%A Ling T. Liu
%A Cecil C. Reames
%T Message communication protocol and operating system design
for the Distributed Loop Computer Network (DLCN)
%J Proceedings of the Fourth Annual International Symposium on Computer Architecture
%D March 1977
%O published as SIGARCH Computer Architecture News 5:7
%K isca isca4
%P 193-200

%A G.H. Pujoulat
%T Architecture of the Corail building block system
%J Proceedings of the Fourth Annual International Symposium on Computer Architecture
%D March 1977
%O published as SIGARCH Computer Architecture News 5:7
%K isca isca4
%P 201-204

%A H.L. Tredennick
%A T.A. Welch
%T High-speed buffering for variable length operands
%J Proceedings of the Fourth Annual International Symposium on Computer Architecture
%D March 1977
%O published as SIGARCH Computer Architecture News 5:7
%K isca isca4
%P 205-209

%A G.S. Miranker
%T A digital signal processor
for real time generation of speech waveforms
%J Proceedings of the Fifth Annual International Symposium on Computer Architecture
%D April 1978
%O published as SIGARCH Computer Architecture News 6:3
%K isca isca5
%P 1-7

%A A. Mukhopadhyay
%T Hardware algorithms for nonnumeric computation
%J Proceedings of the Fifth Annual International Symposium on Computer Architecture
%D April 1978
%O published as SIGARCH Computer Architecture News 6:3
%K isca isca5
%P 8-16

%A A. Huang
%T An optical residue arithmetic unit
%J Proceedings of the Fifth Annual International Symposium on Computer Architecture
%D April 1978
%O published as SIGARCH Computer Architecture News 6:3
%K isca isca5
%P 17-23

%A M.J. Irwin
%T A pipelined processing unit for on-line division
%J Proceedings of the Fifth Annual International Symposium on Computer Architecture
%D April 1978
%O published as SIGARCH Computer Architecture News 6:3
%K isca isca5
%P 24-30

%A G.J. Lipovski
%T Architectural features of CASSM:
a context addressed segment sequential memory
%J Proceedings of the Fifth Annual International Symposium on Computer Architecture
%D April 1978
%O published as SIGARCH Computer Architecture News 6:3
%K isca isca5
%P 31-38

%A L.A. Hollaar
%T Rotating memory processors
for the matching of complex textual patterns
%J Proceedings of the Fifth Annual International Symposium on Computer Architecture
%D April 1978
%O published as SIGARCH Computer Architecture News 6:3
%K isca isca5
%P 39-43

%A K. Kannan
%T The design of a mass memory for a database computer
%J Proceedings of the Fifth Annual International Symposium on Computer Architecture
%D April 1978
%O published as SIGARCH Computer Architecture News 6:3
%K isca isca5
%P 44-51

%A S.A. Schuster
%A H.B. Nguyen
%A E.A. Ozharahan
%A K.C. Smith
%T RAP.2: an associative processor for databases
%J Proceedings of the Fifth Annual International Symposium on Computer Architecture
%D April 1978
%O published as SIGARCH Computer Architecture News 6:3
%K isca isca5
%P 52-59

%A H.J. Burkle
%A A. Frick
%A Ch. Schlier
%T High level language oriented hardware and the post-von Neumann era
%J Proceedings of the Fifth Annual International Symposium on Computer Architecture
%D April 1978
%O published as SIGARCH Computer Architecture News 6:3
%K isca isca5
%P 60-65

%A P. Hibbard
%A A. Hisgen
%A T. Redeheffer
%T A language implementation design for a multiprocessor computer system
%J Proceedings of the Fifth Annual International Symposium on Computer Architecture
%D April 1978
%O published as SIGARCH Computer Architecture News 6:3
%K isca isca5
%P 66-72

%A H.J. Saal
%A I. Gat
%T A hardware architecture for controlling information flow
%J Proceedings of the Fifth Annual International Symposium on Computer Architecture
%D April 1978
%O published as SIGARCH Computer Architecture News 6:3
%K isca isca5
%P 73-77

%A K. Berkling
%T Computer architecture for correct programming
%J Proceedings of the Fifth Annual International Symposium on Computer Architecture
%D April 1978
%O published as SIGARCH Computer Architecture News 6:3
%K isca isca5
%P 78-84

%A E. Maymon
%A D. Tabak
%T Selection of microprocessor equipment
%J Proceedings of the Fifth Annual International Symposium on Computer Architecture
%D April 1978
%O published as SIGARCH Computer Architecture News 6:3
%K isca isca5
%P 85-88

%A L.L. Kinney
%A R.G. Arnold
%T Analysis of a multiprocessor system with a shared bus
%J Proceedings of the Fifth Annual International Symposium on Computer Architecture
%D April 1978
%O published as SIGARCH Computer Architecture News 6:3
%K isca isca5
%P 89-95

%A R.M. Kant
%A T. Kimura
%T Decentralized parallel algorithms for matrix computation
%J Proceedings of the Fifth Annual International Symposium on Computer Architecture
%D April 1978
%O published as SIGARCH Computer Architecture News 6:3
%K isca isca5
%P 96-100

%A R.L. Sites
%T An analysis of the Cray-1 computer
%J Proceedings of the Fifth Annual International Symposium on Computer Architecture
%D April 1978
%O published as SIGARCH Computer Architecture News 6:3
%K isca isca5
%P 101-106

%A G.J. Myers
%T Storage concepts in a software-reliability-directed architecture
%J Proceedings of the Fifth Annual International Symposium on Computer Architecture
%D April 1978
%O published as SIGARCH Computer Architecture News 6:3
%K isca isca5
%P 107-113

%A S.E. Woodard
%A G. Metze
%T Self-checking alternating logic: sequential circuit design
%J Proceedings of the Fifth Annual International Symposium on Computer Architecture
%D April 1978
%O published as SIGARCH Computer Architecture News 6:3
%K isca isca5
%P 114-122

%A L. Boi
%A P. Michel
%T An approach to a fault-tolerant system architecture
%J Proceedings of the Fifth Annual International Symposium on Computer Architecture
%D April 1978
%O published as SIGARCH Computer Architecture News 6:3
%K isca isca5
%P 123-130

%A K.H. Kim
%A C.V. Ramamoorthy
%T Structure of an efficient duplex memory
for processing fault-tolerant programs
%J Proceedings of the Fifth Annual International Symposium on Computer Architecture
%D April 1978
%O published as SIGARCH Computer Architecture News 6:3
%K isca isca5
%P 131-138

%A S.S. Patil
%A T. Welch
%T An approach to using VLSI in digital systems
%J Proceedings of the Fifth Annual International Symposium on Computer Architecture
%D April 1978
%O published as SIGARCH Computer Architecture News 6:3
%K isca isca5
%P 139-143

%A A.M. Despain
%A D.A. Patterson
%T X-tree: a tree structured multi-processor computer architecture
%J Proceedings of the Fifth Annual International Symposium on Computer Architecture
%D April 1978
%O published as SIGARCH Computer Architecture News 6:3
%K isca isca5
%P 144-151

%A P.E. Stanley
%T Address size independence in a 16-bit minicomputer
%J Proceedings of the Fifth Annual International Symposium on Computer Architecture
%D April 1978
%O published as SIGARCH Computer Architecture News 6:3
%K isca isca5
%P 152-158

%A A.C. Parker
%A A. Nagle
%T Description and simulation of microcode execution
%J Proceedings of the Fifth Annual International Symposium on Computer Architecture
%D April 1978
%O published as SIGARCH Computer Architecture News 6:3
%K isca isca5
%P 159-165

%A M. Jino
%A J.W.S. Liu
%T Intelligent magnetic bubble memories
%J Proceedings of the Fifth Annual International Symposium on Computer Architecture
%D April 1978
%O published as SIGARCH Computer Architecture News 6:3
%K isca isca5
%P 166-174

%A W.K. Giloi
%A H.K. Berg
%T Data structure architectures - a major operational principle
%J Proceedings of the Fifth Annual International Symposium on Computer Architecture
%D April 1978
%O published as SIGARCH Computer Architecture News 6:3
%K isca isca5
%P 175-181

%A D.J. DeWitt
%T DIRECT - a multiprocessor organization
for supporting relational data base management systems
%J Proceedings of the Fifth Annual International Symposium on Computer Architecture
%D April 1978
%O published as SIGARCH Computer Architecture News 6:3
%K isca isca5
%P 182-189

%A R.D. Russell
%T The PDP-11: a case study of how not to design condition codes
%J Proceedings of the Fifth Annual International Symposium on Computer Architecture
%D April 1978
%O published as SIGARCH Computer Architecture News 6:3
%K isca isca5
%P 190-194

%A H.K. Reghbati
%A V.C. Hamacher
%T Hardware support for the concurrent programming
in loosely coupled multiprocessors
%J Proceedings of the Fifth Annual International Symposium on Computer Architecture
%D April 1978
%O published as SIGARCH Computer Architecture News 6:3
%K isca isca5
%P 195-201

%A F.A. Briggs
%T Performance of memory configurations for parallel-pipelined computers
%J Proceedings of the Fifth Annual International Symposium on Computer Architecture
%D April 1978
%O published as SIGARCH Computer Architecture News 6:3
%K isca isca5
%P 202-209

%A A.L. Davis
%T The architecture and system method of DDM1:
a recursively structured data driven machine
%J Proceedings of the Fifth Annual International Symposium on Computer Architecture
%D April 1978
%O published as SIGARCH Computer Architecture News 6:3
%K isca isca5
%P 210-215

%A S. Nishikawa
%A M. Sato
%A K. Murakami
%T Interconnection unit for poly-processor system: analysis and design
%J Proceedings of the Fifth Annual International Symposium on Computer Architecture
%D April 1978
%O published as SIGARCH Computer Architecture News 6:3
%K isca isca5
%P 216-222

%A H.J. Siegel
%A S.D. Smith
%T Study of multistage SIMD interconnection networks
%J Proceedings of the Fifth Annual International Symposium on Computer Architecture
%D April 1978
%O published as SIGARCH Computer Architecture News 6:3
%K isca isca5
%P 223-229

%A P. Corsini
%A G. Frosini
%A F. Grandoni
%A G. Galati
%A M. La Manna
%T The serial microprocessor array (SMA):
microprogramming and application examples
%J Proceedings of the Fifth Annual International Symposium on Computer Architecture
%D April 1978
%O published as SIGARCH Computer Architecture News 6:3
%K isca isca5
%P 230-235

%A D. Davies
%T Reliable synchronization in redundant systems
%J Proceedings of the Fifth Annual International Symposium on Computer Architecture
%D April 1978
%O published as SIGARCH Computer Architecture News 6:3
%K isca isca5
%P 236-237
%O synopsis

%A D.F. Towsley
%T The effects of CPU: I/O overlap on computer system configuration
%J Proceedings of the Fifth Annual International Symposium on Computer Architecture
%D April 1978
%O published as SIGARCH Computer Architecture News 6:3
%K isca isca5
%P 238-241

%A A.J. Smith
%T On the effectiveness of buffered and multiple arm disks
%J Proceedings of the Fifth Annual International Symposium on Computer Architecture
%D April 1978
%O published as SIGARCH Computer Architecture News 6:3
%K isca isca5
%P 242-248

%A J.H. Patel
%T Pipelines with internal buffers
%J Proceedings of the Fifth Annual International Symposium on Computer Architecture
%D April 1978
%O published as SIGARCH Computer Architecture News 6:3
%K isca isca5
%P 249-254

%A E.P. Farrell
%A N. Ghani
%A P.C. Treleaven
%T A concurrent computer architecture and a ring based implementation
%J Proceedings of the Sixth Annual International Symposium on Computer Architecture
%C Philadelphia
%D April 1979
%O published as SIGARCH Computer Architecture News 7:3
%K isca isca6
%P 1-11

%A R.M. Owens
%A M.J. Irwin
%T On-line algorithms for the design of pipeline architectures
%J Proceedings of the Sixth Annual International Symposium on Computer Architecture
%C Philadelphia
%D April 1979
%O published as SIGARCH Computer Architecture News 7:3
%K isca isca6
%P 12-19

%A V.D. Gligor
%T Architectural implementations of abstract data type implementation
%J Proceedings of the Sixth Annual International Symposium on Computer Architecture
%C Philadelphia
%D April 1979
%O published as SIGARCH Computer Architecture News 7:3
%K isca isca6
%P 20-30

%A K. Sakamura
%A K. Nakano
%A Y. Kato
%A H. Aiso
%T A new approach to an adaptive computer - an automatic
recovery mechanism to prevent the occurrence of subtract errors
%J Proceedings of the Sixth Annual International Symposium on Computer Architecture
%C Philadelphia
%D April 1979
%O published as SIGARCH Computer Architecture News 7:3
%K isca isca6
%P 31-41

%A A. Brandwajn
%A J.A. Hernandez
%A R. Joly
%A P. Kruchten
%T Overview of the ARCADE system
%J Proceedings of the Sixth Annual International Symposium on Computer Architecture
%C Philadelphia
%D April 1979
%O published as SIGARCH Computer Architecture News 7:3
%K isca isca6
%P 42-49

%A R.B. Dannenberg
%T An architecture with many operand registers
to efficiently execute block-structured languages
%J Proceedings of the Sixth Annual International Symposium on Computer Architecture
%C Philadelphia
%D April 1979
%O published as SIGARCH Computer Architecture News 7:3
%K isca isca6
%P 50-57

%A H. Fuchs
%A B.W. Johnson
%T An expanded multiprocessor architecture for video graphics
%J Proceedings of the Sixth Annual International Symposium on Computer Architecture
%C Philadelphia
%D April 1979
%O published as SIGARCH Computer Architecture News 7:3
%K isca isca6
%P 58-67

%A C.V.W. Armstrong
%A N.A. Brans
%A H.M. Ahmed
%T An adaptive multimicroprocessor array computing structure
for radar signal processing applications
%J Proceedings of the Sixth Annual International Symposium on Computer Architecture
%C Philadelphia
%D April 1979
%O published as SIGARCH Computer Architecture News 7:3
%K isca isca6
%P 68-74

%A B.D. Ackland
%T A bit-slice cache controller
%J Proceedings of the Sixth Annual International Symposium on Computer Architecture
%C Philadelphia
%D April 1979
%O published as SIGARCH Computer Architecture News 7:3
%K isca isca6
%P 75-82

%A J.A. Harris
%A D.R. Smith
%T Simulation experiments on a tree organized minicomputer
%J Proceedings of the Sixth Annual International Symposium on Computer Architecture
%C Philadelphia
%D April 1979
%O published as SIGARCH Computer Architecture News 7:3
%K isca isca6
%P 83-89

%A D.A. Patterson
%A E.S. Fehr
%A C.H. Sequin
%T Design considerations for the VLSI processor of X-tree
%J Proceedings of the Sixth Annual International Symposium on Computer Architecture
%C Philadelphia
%D April 1979
%O published as SIGARCH Computer Architecture News 7:3
%K isca isca6
%P 90-101

%A E. Goto
%A T. Ida
%A K. Hiraki
%T FLATS, a machine for numerical, symbolic, and associative computing
%J Proceedings of the Sixth Annual International Symposium on Computer Architecture
%C Philadelphia
%D April 1979
%O published as SIGARCH Computer Architecture News 7:3
%K isca isca6
%P 102-110

%A J. Spragins
%A T. Lewis
%A H. Jafari
%T Some simplified performance modeling techniques
with applications to a new ring-structured microcomputer network
%J Proceedings of the Sixth Annual International Symposium on Computer Architecture
%C Philadelphia
%D April 1979
%O published as SIGARCH Computer Architecture News 7:3
%K isca isca6
%P 111-116

%A K.S. Trivedi
%A T.M. Sigmon
%T A performance comparison of optimally designed computer systems
with and without virtual memory
%J Proceedings of the Sixth Annual International Symposium on Computer Architecture
%C Philadelphia
%D April 1979
%O published as SIGARCH Computer Architecture News 7:3
%K isca isca6
%P 117-121

%A T.K. Agerwala
%A K.M. Cahndy
%A D.E. Lang
%T A modeling approach and design tool for pipelined central processors
%J Proceedings of the Sixth Annual International Symposium on Computer Architecture
%C Philadelphia
%D April 1979
%O published as SIGARCH Computer Architecture News 7:3
%K isca isca6
%P 122-129

%A M. Sato
%A S. Nichikawa
%A K. Murakami
%A S. Takahira
%T Dynamic function exchanging mechanism in poly-processor system
%J Proceedings of the Sixth Annual International Symposium on Computer Architecture
%C Philadelphia
%D April 1979
%O published as SIGARCH Computer Architecture News 7:3
%K isca isca6
%P 130-136

%A B.R. Borgerson
%A M.D. Godfrey
%A P.E. Hagerty
%A T.R. Rykken
%T The architecture of Sperry Univax 1100 series systems
%J Proceedings of the Sixth Annual International Symposium on Computer Architecture
%C Philadelphia
%D April 1979
%O published as SIGARCH Computer Architecture News 7:3
%K isca isca6
%P 137-146

%A H.K. Reghbati
%T An efficient time-shared link processor
for supporting computer in parallel systems with dynamic structure
%J Proceedings of the Sixth Annual International Symposium on Computer Architecture
%C Philadelphia
%D April 1979
%O published as SIGARCH Computer Architecture News 7:3
%K isca isca6
%P 147-159

%A A.R. Tripathi
%A G.J. Lipovski
%T Packet switching in Banyan networks
%J Proceedings of the Sixth Annual International Symposium on Computer Architecture
%C Philadelphia
%D April 1979
%O published as SIGARCH Computer Architecture News 7:3
%K isca isca6
%P 160-167

%A J.H. Patel
%T Processor-memory interconnections for multiprocessors
%J Proceedings of the Sixth Annual International Symposium on Computer Architecture
%C Philadelphia
%D April 1979
%O published as SIGARCH Computer Architecture News 7:3
%K isca isca6
%P 168-177

%A B.I. Strom
%T Proof of the equivalent realizability of a time-bound arbiter
and a runt-free inertial delay
%J Proceedings of the Sixth Annual International Symposium on Computer Architecture
%C Philadelphia
%D April 1979
%O published as SIGARCH Computer Architecture News 7:3
%K isca isca6
%P 178-181

%A M.A. Franklin
%A S.A. Kahn
%A M.J. Stucki
%T Design issues in the development
of a modular multiprocessor communications network
%J Proceedings of the Sixth Annual International Symposium on Computer Architecture
%C Philadelphia
%D April 1979
%O published as SIGARCH Computer Architecture News 7:3
%K isca isca6
%P 182-187

%A M. Maekawa
%A I. Yamazaki
%A A. Maeda
%A M. Miyata
%A S. Kamiya
%A H. Kasai
%T Experimental polyprocessor system (EPOS) - architecture
%J Proceedings of the Sixth Annual International Symposium on Computer Architecture
%C Philadelphia
%D April 1979
%O published as SIGARCH Computer Architecture News 7:3
%K isca isca6
%P 188-195

%A M. Maekawa
%A I. Yamazaki
%A A. Tanaka
%A A. Nakamura
%A K. Itsida
%T Experimental polyprocessor system (EPOS) - operating system
%J Proceedings of the Sixth Annual International Symposium on Computer Architecture
%C Philadelphia
%D April 1979
%O published as SIGARCH Computer Architecture News 7:3
%K isca isca6
%P 196-201

%A T. Feng
%A C. Wu
%A D.P. Agrawal
%T A microprocessor-controlled asynchronous circuit switching network
%J Proceedings of the Sixth Annual International Symposium on Computer Architecture
%C Philadelphia
%D April 1979
%O published as SIGARCH Computer Architecture News 7:3
%K isca isca6
%P 202-215

%A W.G. Rosocha
%A E.S. Lee
%T Performance enhancement fo SISD processors
%J Proceedings of the Sixth Annual International Symposium on Computer Architecture
%C Philadelphia
%D April 1979
%O published as SIGARCH Computer Architecture News 7:3
%K isca isca6
%P 216-231

%A S.D. Smith
%A H.J. Siegel
%T An emulator network for SIMD machine interconnection networks
%J Proceedings of the Sixth Annual International Symposium on Computer Architecture
%C Philadelphia
%D April 1979
%O published as SIGARCH Computer Architecture News 7:3
%K isca isca6
%P 232-241

%A J.B. Dennis
%A G.A. Boughton
%A C.K.C. Leung
%T Building blocks for data flow prototypes
%J Proceedings of the Seventh Annual International Symposium on Computer Architecture
%C La Baule, France
%D May 1980
%O published as SIGARCH Computer Architecture News 8:3
%K isca isca7
%P 1-8

%A E.S. Davidson
%T A multiple stream microprocessor prototype system: AMP-1
%J Proceedings of the Seventh Annual International Symposium on Computer Architecture
%C La Baule, France
%D May 1980
%O published as SIGARCH Computer Architecture News 8:3
%K isca isca7
%P 9-16

%A E. Andre
%A J.P. Banatre
%A H. Leroy
%A G. Paget
%A F. Ployette
%A J.P. Routeau
%T Kensur: an architecture oriented towards
programming languages translation
%J Proceedings of the Seventh Annual International Symposium on Computer Architecture
%C La Baule, France
%D May 1980
%O published as SIGARCH Computer Architecture News 8:3
%K isca isca7
%P 17-22

%A J.G. Kuhl
%A S.M. Reddy
%T Distributed fault-tolerant for large multiprocessor systems
%J Proceedings of the Seventh Annual International Symposium on Computer Architecture
%C La Baule, France
%D May 1980
%O published as SIGARCH Computer Architecture News 8:3
%K isca isca7
%P 23-30

%A M. Malek
%T A comparison connection assignment
for diagnosis of multiprocessor systems
%J Proceedings of the Seventh Annual International Symposium on Computer Architecture
%C La Baule, France
%D May 1980
%O published as SIGARCH Computer Architecture News 8:3
%K isca isca7
%P 31-36

%A K.E. Grosspietsch
%A J. Kaiser
%A E. Nett
%T A concept for test and reconfiguration
of a fault-tolerant VLSI processor system
%J Proceedings of the Seventh Annual International Symposium on Computer Architecture
%C La Baule, France
%D May 1980
%O published as SIGARCH Computer Architecture News 8:3
%K isca isca7
%P 37-43

%A J.-P. Brassard
%A J. Gecsel
%T Path building in cellular partitioning networks
%J Proceedings of the Seventh Annual International Symposium on Computer Architecture
%C La Baule, France
%D May 1980
%O published as SIGARCH Computer Architecture News 8:3
%K isca isca7
%P 44-50

%A R.J. McMillen
%A H.J. Siegel
%T MIMD machine communication
using the augmented data manipulator network
%J Proceedings of the Seventh Annual International Symposium on Computer Architecture
%C La Baule, France
%D May 1980
%O published as SIGARCH Computer Architecture News 8:3
%K isca isca7
%P 51-60

%A J.P. Shen
%A J.P. Hayes
%T Fault tolerance of a class of connection networks
%J Proceedings of the Seventh Annual International Symposium on Computer Architecture
%C La Baule, France
%D May 1980
%O published as SIGARCH Computer Architecture News 8:3
%K isca isca7
%P 61-71

%A E.G. Coffman Jr
%A K. So
%T On the comparison between single and multiple processor systems
%J Proceedings of the Seventh Annual International Symposium on Computer Architecture
%C La Baule, France
%D May 1980
%O published as SIGARCH Computer Architecture News 8:3
%K isca isca7
%P 72-79

%A V.C. Hamacher
%A G.S. Shedler
%T Performance of a collision-free local bus network
having asynchronous distributed control
%J Proceedings of the Seventh Annual International Symposium on Computer Architecture
%C La Baule, France
%D May 1980
%O published as SIGARCH Computer Architecture News 8:3
%K isca isca7
%P 80-87

%A W.M. Zuberek
%T Timed Petri nets and preliminary performance evaluation
%J Proceedings of the Seventh Annual International Symposium on Computer Architecture
%C La Baule, France
%D May 1980
%O published as SIGARCH Computer Architecture News 8:3
%K isca isca7
%P 88-96

%A D.R. Ditzel
%A D.A. Patterson
%T Retrospective on high-level language computer architecture
%J Proceedings of the Seventh Annual International Symposium on Computer Architecture
%C La Baule, France
%D May 1980
%O published as SIGARCH Computer Architecture News 8:3
%K isca isca7
%P 97-104

%A J.P. Sansonnet
%A M. Castan
%A C. Percebois
%T M3L: a list-directed architecture
%J Proceedings of the Seventh Annual International Symposium on Computer Architecture
%C La Baule, France
%D May 1980
%O published as SIGARCH Computer Architecture News 8:3
%K isca isca7
%P 105-112

%A Y. Hibino
%T A practical parallel garbage collection algorithm
and its implementation
%J Proceedings of the Seventh Annual International Symposium on Computer Architecture
%C La Baule, France
%D May 1980
%O published as SIGARCH Computer Architecture News 8:3
%K isca isca7
%P 113-120

%A P.C. Treleaven
%A G.F. Mole
%T A multi-processor reduction machine
for user-defined reduction languages
%J Proceedings of the Seventh Annual International Symposium on Computer Architecture
%C La Baule, France
%D May 1980
%O published as SIGARCH Computer Architecture News 8:3
%K isca isca7
%P 121-130

%A J.M. Toblas
%T A single user multiprocessor
incorporating processor manipulation facilities
%J Proceedings of the Seventh Annual International Symposium on Computer Architecture
%C La Baule, France
%D May 1980
%O published as SIGARCH Computer Architecture News 8:3
%K isca isca7
%P 131-138

%A R.H. Halstead Jr
%A S.A. Ward
%T The MUNET: a scalable decentralized architecture
for parallel computation
%J Proceedings of the Seventh Annual International Symposium on Computer Architecture
%C La Baule, France
%D May 1980
%O published as SIGARCH Computer Architecture News 8:3
%K isca isca7
%P 139-145

%A B.W. Lampson
%A K.A. Pier
%T A processor for a high-performance personal computer
%J Proceedings of the Seventh Annual International Symposium on Computer Architecture
%C La Baule, France
%D May 1980
%O published as SIGARCH Computer Architecture News 8:3
%K isca isca7
%P 146-160

%A D.B.G. Edwards
%A A.E. Knowles
%A J.V. Woods
%T MU6-G: a new design to achieve mainframe performance
from a mini-sized computer
%J Proceedings of the Seventh Annual International Symposium on Computer Architecture
%C La Baule, France
%D May 1980
%O published as SIGARCH Computer Architecture News 8:3
%K isca isca7
%P 161-167

%A K.E. Batcher
%T Architecture of a massively parallel processor
%J Proceedings of the Seventh Annual International Symposium on Computer Architecture
%C La Baule, France
%D May 1980
%O published as SIGARCH Computer Architecture News 8:3
%K isca isca7
%P 168-173

%A J. Palmer
%T The Intel 8087 numeric data processor
%J Proceedings of the Seventh Annual International Symposium on Computer Architecture
%C La Baule, France
%D May 1980
%O published as SIGARCH Computer Architecture News 8:3
%K isca isca7
%P 174-181

%A R.H. Kuhn
%T Efficient mapping of algorithms to single-stage interconnections
%J Proceedings of the Seventh Annual International Symposium on Computer Architecture
%C La Baule, France
%D May 1980
%O published as SIGARCH Computer Architecture News 8:3
%K isca isca7
%P 182-189

%A D. Nassimi
%A S. Sahni
%T A self routing Benes network
%J Proceedings of the Seventh Annual International Symposium on Computer Architecture
%C La Baule, France
%D May 1980
%O published as SIGARCH Computer Architecture News 8:3
%K isca isca7
%P 190-195

%A H. von Issendorf
%A W. Grunewald
%T An adaptable network for functional distributed systems
%J Proceedings of the Seventh Annual International Symposium on Computer Architecture
%C La Baule, France
%D May 1980
%O published as SIGARCH Computer Architecture News 8:3
%K isca isca7
%P 196-201

%A M.B. Riad
%T A combination of field and current access techniques
for efficient and cost-effective bubble memories
%J Proceedings of the Seventh Annual International Symposium on Computer Architecture
%C La Baule, France
%D May 1980
%O published as SIGARCH Computer Architecture News 8:3
%K isca isca7
%P 202-210

%A K.S. Trivedi
%T Designing linear storage hierarchies so as to maximize reliability
subject to cost and performance constraints
%J Proceedings of the Seventh Annual International Symposium on Computer Architecture
%C La Baule, France
%D May 1980
%O published as SIGARCH Computer Architecture News 8:3
%K isca isca7
%P 211-217

%A S.R. Ahuja
%A C.S. Roberts
%T An associative/parallel processor for partial match retrieval
using superimposed codes
%J Proceedings of the Seventh Annual International Symposium on Computer Architecture
%C La Baule, France
%D May 1980
%O published as SIGARCH Computer Architecture News 8:3
%K isca isca7
%P 218-227

%A M.D. Ruggiero
%A S.G. Zaky
%T A microprocessor-based virtual memory system
%J Proceedings of the Seventh Annual International Symposium on Computer Architecture
%C La Baule, France
%D May 1980
%O published as SIGARCH Computer Architecture News 8:3
%K isca isca7
%P 228-235

%A A. Jagannathan
%T A technique for the architectural implementation
of software subsystems
%J Proceedings of the Seventh Annual International Symposium on Computer Architecture
%C La Baule, France
%D May 1980
%O published as SIGARCH Computer Architecture News 8:3
%K isca isca7
%P 236-244

%A V. Berstis
%T Security and protection of data in the IBM System/38
%J Proceedings of the Seventh Annual International Symposium on Computer Architecture
%C La Baule, France
%D May 1980
%O published as SIGARCH Computer Architecture News 8:3
%K isca isca7
%P 245-252

%A M.G. Hoffman
%T Hardware implementation of communication protocols: a formal approach
%J Proceedings of the Seventh Annual International Symposium on Computer Architecture
%C La Baule, France
%D May 1980
%O published as SIGARCH Computer Architecture News 8:3
%K isca isca7
%P 253-263

%A P. Gillier
%A D. Slosberg
%T An architecture with comprehensive facilities
of inter-process synchronization and communication
%J Proceedings of the Seventh Annual International Symposium on Computer Architecture
%C La Baule, France
%D May 1980
%O published as SIGARCH Computer Architecture News 8:3
%K isca isca7
%P 264-270

%A R.M. Lougheed
%A D.L. McCubbrey
%T The cytocomputer: a practical pipelined image processor
%J Proceedings of the Seventh Annual International Symposium on Computer Architecture
%C La Baule, France
%D May 1980
%O published as SIGARCH Computer Architecture News 8:3
%K isca isca7
%P 271-277

%A C. Halatsis
%A A. van Dam
%A J. Joosten
%A M. Letheren
%T Architectural considerations for a microprogrammable emulating engine
using bit-slices
%J Proceedings of the Seventh Annual International Symposium on Computer Architecture
%C La Baule, France
%D May 1980
%O published as SIGARCH Computer Architecture News 8:3
%K isca isca7
%P 278-291

%A M.J. Irwin
%A D. Heller
%T Online pipeline systems for recursive numeric computations
%J Proceedings of the Seventh Annual International Symposium on Computer Architecture
%C La Baule, France
%D May 1980
%O published as SIGARCH Computer Architecture News 8:3
%K isca isca7
%P 292-299

%A M.J. Foster
%A H.T. Kung
%T Design of special-purpose VLSI chips: example and opinions
%J Proceedings of the Seventh Annual International Symposium on Computer Architecture
%C La Baule, France
%D May 1980
%O published as SIGARCH Computer Architecture News 8:3
%K isca isca7
%P 300-307

%A A. Kumar
%A P.C.P. Bhatt
%T A structured language for CAD of digital systems
%J Proceedings of the Seventh Annual International Symposium on Computer Architecture
%C La Baule, France
%D May 1980
%O published as SIGARCH Computer Architecture News 8:3
%K isca isca7
%P 308-316

%A U. Hecksen
%A R. Klar
%A W. Kleinoder
%T Hardware-measurements of storage access conflicts
in the processor array EGPA
%J Proceedings of the Seventh Annual International Symposium on Computer Architecture
%C La Baule, France
%D May 1980
%O published as SIGARCH Computer Architecture News 8:3
%K isca isca7
%P 317-324

%A M. Tokoro
%A K. Tamaru
%A M. Misuno
%A M. Hori
%T A high level multi-lingual multiprocessor KMP
%J Proceedings of the Seventh Annual International Symposium on Computer Architecture
%C La Baule, France
%D May 1980
%O published as SIGARCH Computer Architecture News 8:3
%K isca isca7
%P 325-333

%A B.W. Arden
%A R. Ginosar
%T MP/C: a multiprocessor/computer architecture
%J Proceedings of the Eighth Annual International Symposium on Computer Architecture
%C Minneapolis, Minnesota
%D May 1981
%O published as SIGARCH Computer Architecture News 9:3
%K isca isca8
%P 3-20

%A D.P. Agrawal
%T A pipelined pseudoparallel system architecture for motion analysis
%J Proceedings of the Eighth Annual International Symposium on Computer Architecture
%C Minneapolis, Minnesota
%D May 1981
%O published as SIGARCH Computer Architecture News 9:3
%K isca isca8
%P 21-36

%A R.F. Hobson
%T Structured machine design: an ongoing experiment
%J Proceedings of the Eighth Annual International Symposium on Computer Architecture
%C Minneapolis, Minnesota
%D May 1981
%O published as SIGARCH Computer Architecture News 9:3
%K isca isca8
%P 37-55

%A R. Jenevein
%A D. DeGroot
%A G.J. Lipovski
%T A hardware support mechanism for scheduling resources
in a parallel machine environment
%J Proceedings of the Eighth Annual International Symposium on Computer Architecture
%C Minneapolis, Minnesota
%D May 1981
%O published as SIGARCH Computer Architecture News 9:3
%K isca isca8
%P 57-66

%A F. Briggs
%A M. Dubois
%A K. Hwang
%T Throughput analysis and configuration design
of a shared-resource multiprocessor system: PUMPS
%J Proceedings of the Eighth Annual International Symposium on Computer Architecture
%C Minneapolis, Minnesota
%D May 1981
%O published as SIGARCH Computer Architecture News 9:3
%K isca isca8
%P 67-80

%A D. Kroft
%T Lockup-free instruction fetch/prefetch cache organization
%J Proceedings of the Eighth Annual International Symposium on Computer Architecture
%C Minneapolis, Minnesota
%D May 1981
%O published as SIGARCH Computer Architecture News 9:3
%K isca isca8
%P 81-87

%A W.C. Yen
%A K.S. Fu
%T Analysis of multiprocessor cache organizations
with alternative main memory update policies
%J Proceedings of the Eighth Annual International Symposium on Computer Architecture
%C Minneapolis, Minnesota
%D May 1981
%O published as SIGARCH Computer Architecture News 9:3
%K isca isca8
%P 89-106

%A W.L. Bain Jr
%A S.R. Ahuja
%T Performance analysis of high-speed digital buses
for multiprocessing systems
%J Proceedings of the Eighth Annual International Symposium on Computer Architecture
%C Minneapolis, Minnesota
%D May 1981
%O published as SIGARCH Computer Architecture News 9:3
%K isca isca8
%P 107-134

%A J.E. Smith
%T A study of branch prediction strategies
%J Proceedings of the Eighth Annual International Symposium on Computer Architecture
%C Minneapolis, Minnesota
%D May 1981
%O published as SIGARCH Computer Architecture News 9:3
%K isca isca8
%P 135-148

%A A. Gallo
%A R.P. Wilder
%T Performance measurement of data communication systems
with emphasis on open systems interconnections (OSI)
%J Proceedings of the Eighth Annual International Symposium on Computer Architecture
%C Minneapolis, Minnesota
%D May 1981
%O published as SIGARCH Computer Architecture News 9:3
%K isca isca8
%P 149-161

%A G.W. Geitz
%A E.J. Schmitter
%T BFS - realization of a fault-tolerant architecture
%J Proceedings of the Eighth Annual International Symposium on Computer Architecture
%C Minneapolis, Minnesota
%D May 1981
%O published as SIGARCH Computer Architecture News 9:3
%K isca isca8
%P 163-170

%A M. Maekawa
%T Optimal processor interconnection topologies
%J Proceedings of the Eighth Annual International Symposium on Computer Architecture
%C Minneapolis, Minnesota
%D May 1981
%O published as SIGARCH Computer Architecture News 9:3
%K isca isca8
%P 171-186

%A M. Dubois
%A F. Briggs
%T Efficient interprocessor communication
for MIMD multiprocessor systems
%J Proceedings of the Eighth Annual International Symposium on Computer Architecture
%C Minneapolis, Minnesota
%D May 1981
%O published as SIGARCH Computer Architecture News 9:3
%K isca isca8
%P 187-196

%A B. Ackland
%A N. Weste
%A D.J. Burr
%T An integrated multiprocessing array for time warp pattern matching
%J Proceedings of the Eighth Annual International Symposium on Computer Architecture
%C Minneapolis, Minnesota
%D May 1981
%O published as SIGARCH Computer Architecture News 9:3
%K isca isca8
%P 197-216

%A N.R. Greenfeld
%T Jericho: a professional's personal computer system
%J Proceedings of the Eighth Annual International Symposium on Computer Architecture
%C Minneapolis, Minnesota
%D May 1981
%O published as SIGARCH Computer Architecture News 9:3
%K isca isca8
%P 217-226

%A B.W. Arden
%A R. Ginosar
%T A single-relation module for a data base machine
%J Proceedings of the Eighth Annual International Symposium on Computer Architecture
%C Minneapolis, Minnesota
%D May 1981
%O published as SIGARCH Computer Architecture News 9:3
%K isca isca8
%P 227-237

%A B.W. Wah
%A Y.W. Ma
%T MANIP - A parallel computer system
for implementing branch and bound algorithms
%J Proceedings of the Eighth Annual International Symposium on Computer Architecture
%C Minneapolis, Minnesota
%D May 1981
%O published as SIGARCH Computer Architecture News 9:3
%K isca isca8
%P 239-262

%A P.I. Georgiadis
%A M.P. Papazoglou
%A D.G. Maritsas
%T Towards a parallel SIMULA machine
%J Proceedings of the Eighth Annual International Symposium on Computer Architecture
%C Minneapolis, Minnesota
%D May 1981
%O published as SIGARCH Computer Architecture News 9:3
%K isca isca8
%P 263-278

%A P.C. Treleaven
%A R.P. Hopkins
%T Decentralized computation
%J Proceedings of the Eighth Annual International Symposium on Computer Architecture
%C Minneapolis, Minnesota
%D May 1981
%O published as SIGARCH Computer Architecture News 9:3
%K isca isca8
%P 279-290

%A Arvind
%A V. Kathail
%T A multiple processor data flow machine
that supports generalized procedures
%J Proceedings of the Eighth Annual International Symposium on Computer Architecture
%C Minneapolis, Minnesota
%D May 1981
%O published as SIGARCH Computer Architecture News 9:3
%K isca isca8
%P 291-302

%A V.P. Srini
%T An architecture for extended abstract data flow
%J Proceedings of the Eighth Annual International Symposium on Computer Architecture
%C Minneapolis, Minnesota
%D May 1981
%O published as SIGARCH Computer Architecture News 9:3
%K isca isca8
%P 303-326

%A F.J. Burkowski
%T A multi-user data flow architecture
%J Proceedings of the Eighth Annual International Symposium on Computer Architecture
%C Minneapolis, Minnesota
%D May 1981
%O published as SIGARCH Computer Architecture News 9:3
%K isca isca8
%P 327-340

%A M.E. Houdek
%A F.G. Soltis
%A R.L. Hoffman
%T IBM System/38 support for capability-based addressing
%J Proceedings of the Eighth Annual International Symposium on Computer Architecture
%C Minneapolis, Minnesota
%D May 1981
%O published as SIGARCH Computer Architecture News 9:3
%K isca isca8
%P 341-348

%A P. Xia
%A X. Fang
%A Y. Wang
%A G. Wang
%A Y. Liu
%A C. Li
%A C. Lin
%A W. Zan
%A Q. Sun
%T An array processor for petroleum exploration
%J Proceedings of the Eighth Annual International Symposium on Computer Architecture
%C Minneapolis, Minnesota
%D May 1981
%O published as SIGARCH Computer Architecture News 9:3
%K isca isca8
%P 349-354

%A K.E. MacKenzie
%T On refuting the creation theory of computer architecture
%J Proceedings of the Eighth Annual International Symposium on Computer Architecture
%C Minneapolis, Minnesota
%D May 1981
%O published as SIGARCH Computer Architecture News 9:3
%K isca isca8
%P 355
%O abstract only

%A J.E. Thornton
%T Heterogeneous computer architecture
%J Proceedings of the Eighth Annual International Symposium on Computer Architecture
%C Minneapolis, Minnesota
%D May 1981
%O published as SIGARCH Computer Architecture News 9:3
%K isca isca8
%P 355
%O abstract only

%A R.J. Souza
%A E.E. Balkovich
%T Impact of hardware interconnection structures
on the performance of decentralized software
%J Proceedings of the Eighth Annual International Symposium on Computer Architecture
%C Minneapolis, Minnesota
%D May 1981
%O published as SIGARCH Computer Architecture News 9:3
%K isca isca8
%P 357-366

%A M. Hasegawa
%A T. Nakamura
%A Y. Shigei
%T Distributed communicating media - a multitrack bus -
capable of concurrent data exchanging
%J Proceedings of the Eighth Annual International Symposium on Computer Architecture
%C Minneapolis, Minnesota
%D May 1981
%O published as SIGARCH Computer Architecture News 9:3
%K isca isca8
%P 367-372

%A S.K. Arora
%A S.R. Dumpala
%A K.C. Smith
%T WCRC: an ANSI SPARC machine architecture for data base management
%J Proceedings of the Eighth Annual International Symposium on Computer Architecture
%C Minneapolis, Minnesota
%D May 1981
%O published as SIGARCH Computer Architecture News 9:3
%K isca isca8
%P 373-388

%A K. Seo
%A A. Minematsu
%A H. Aiso
%A N. Kamibayashi
%T A look-ahead data staging architecture
for relational data base machines
%J Proceedings of the Eighth Annual International Symposium on Computer Architecture
%C Minneapolis, Minnesota
%D May 1981
%O published as SIGARCH Computer Architecture News 9:3
%K isca isca8
%P 389-406

%A Y. Kiyoki
%A K. Tanaka
%A H. Aiso
%A N. Kamibayashi
%T Design and evaluation of a relational data base machine
employing advanced data structures and algorithms
%J Proceedings of the Eighth Annual International Symposium on Computer Architecture
%C Minneapolis, Minnesota
%D May 1981
%O published as SIGARCH Computer Architecture News 9:3
%K isca isca8
%P 407-423

%A I. Koren
%T A reconfigurable and fault-tolerant VLSI multiprocessor array
%J Proceedings of the Eighth Annual International Symposium on Computer Architecture
%C Minneapolis, Minnesota
%D May 1981
%O published as SIGARCH Computer Architecture News 9:3
%K isca isca8
%P 425-442

%A D.A. Patterson
%A C.H. Sequin
%T RISC I: a reduced instruction set computer
%J Proceedings of the Eighth Annual International Symposium on Computer Architecture
%C Minneapolis, Minnesota
%D May 1981
%O published as SIGARCH Computer Architecture News 9:3
%K isca isca8
%P 443-458

%A L.L. Kinney
%A W.Y. Yueh
%A W.L. Heimerdinger
%A R.R. Ramseyer
%A J.W. Thomas
%T An architecture for a VHSIC computer
%J Proceedings of the Eighth Annual International Symposium on Computer Architecture
%C Minneapolis, Minnesota
%D May 1981
%O published as SIGARCH Computer Architecture News 9:3
%K isca isca8
%P 459-470

%A C.H. Sequin
%T Doubly twisted torus networks for VLSI processor arrays
%J Proceedings of the Eighth Annual International Symposium on Computer Architecture
%C Minneapolis, Minnesota
%D May 1981
%O published as SIGARCH Computer Architecture News 9:3
%K isca isca8
%P 471-480

%A W.K. Giloi
%A P. Behr
%T An IPC protocol and its hardware realization
for a high-speed distributed multicomputer system
%J Proceedings of the Eighth Annual International Symposium on Computer Architecture
%C Minneapolis, Minnesota
%D May 1981
%O published as SIGARCH Computer Architecture News 9:3
%K isca isca8
%P 481-494

%A Z. Chuang-qi
%A S. Ren-Ben
%T Alignment network used for connecting a prime number of
memory blocks with a power of 2 of processing elements
%J Proceedings of the Eighth Annual International Symposium on Computer Architecture
%C Minneapolis, Minnesota
%D May 1981
%O published as SIGARCH Computer Architecture News 9:3
%K isca isca8
%P 495-500

%A R.M. Needham
%T Design considerations for a processing server
%J Proceedings of the Eighth Annual International Symposium on Computer Architecture
%C Minneapolis, Minnesota
%D May 1981
%O published as SIGARCH Computer Architecture News 9:3
%K isca isca8
%P 501-504

%A R.J. McMillen
%T Dynamic rerouting tag schemes
for the augmented data manipulator network
%J Proceedings of the Eighth Annual International Symposium on Computer Architecture
%C Minneapolis, Minnesota
%D May 1981
%O published as SIGARCH Computer Architecture News 9:3
%K isca isca8
%P 505-516

%A D.A. Patterson
%A R.S. Piepho
%T RISC assessment: a high-level language experiment
%J Proceedings of the Ninth Annual International Symposium on Computer Architecture
%C Austin, Texas
%D April 1982
%O published as SIGARCH Computer Architecture News 10:3
%K isca isca9
%P 3-8

%A D.W. Clark
%A H.M. Levy
%T Measurement and analysis of instruction use in the VAX 11-780
%J Proceedings of the Ninth Annual International Symposium on Computer Architecture
%C Austin, Texas
%D April 1982
%O published as SIGARCH Computer Architecture News 10:3
%K isca isca9
%P 9-17

%A K. Kavi
%A B. Belkhouche
%A E. Bullard
%A L. Delcambre
%A S. Nemecek
%T Hll architectures: pitfalls and predilections
%J Proceedings of the Ninth Annual International Symposium on Computer Architecture
%C Austin, Texas
%D April 1982
%O published as SIGARCH Computer Architecture News 10:3
%K isca isca9
%P 18-23

%A A. Gottlieb
%A R. Grishman
%A C.P. Kruskal
%A K.P. McAuliffe
%A L. Rudolph
%A M. Snir
%T The NYU ultracomputer -
designing a MIMD, shared-memory parallel machine
%J Proceedings of the Ninth Annual International Symposium on Computer Architecture
%C Austin, Texas
%D April 1982
%O published as SIGARCH Computer Architecture News 10:3
%K isca isca9
%P 27-42

%A K.H. Chou
%A K.S. Fu
%T VLSI architectures for high-speed recognition
of context-free languages
%J Proceedings of the Ninth Annual International Symposium on Computer Architecture
%C Austin, Texas
%D April 1982
%O published as SIGARCH Computer Architecture News 10:3
%K isca isca9
%P 43-49

%A M. Franklin
%A D. Wann
%T Asynchronous and clocked control structures
for VLSI based interconnection networks
%J Proceedings of the Ninth Annual International Symposium on Computer Architecture
%C Austin, Texas
%D April 1982
%O published as SIGARCH Computer Architecture News 10:3
%K isca isca9
%P 50-59

%A R.J. Macmillen
%A H.J. Siegel
%T Performance and fault tolerance improvements
in the inverse augmented data manipulator network
%J Proceedings of the Ninth Annual International Symposium on Computer Architecture
%C Austin, Texas
%D April 1982
%O published as SIGARCH Computer Architecture News 10:3
%K isca isca9
%P 63-72

%A D.S. Parker
%A C.S. Raghavendra
%T The Gamma network: a multiprocessor interconnection network
with redundant paths
%J Proceedings of the Ninth Annual International Symposium on Computer Architecture
%C Austin, Texas
%D April 1982
%O published as SIGARCH Computer Architecture News 10:3
%K isca isca9
%P 73-80

%A R.M. Jenevein
%A J.C. Browne
%T A control processor for a reconfigurable array computer
%J Proceedings of the Ninth Annual International Symposium on Computer Architecture
%C Austin, Texas
%D April 1982
%O published as SIGARCH Computer Architecture News 10:3
%K isca isca9
%P 81-89

%A L. Bhuyan
%A D.P. Agrawal
%T A general class of processor interconnection strategies
%J Proceedings of the Ninth Annual International Symposium on Computer Architecture
%C Austin, Texas
%D April 1982
%O published as SIGARCH Computer Architecture News 10:3
%K isca isca9
%P 90-98

%A F.J. Burkowski
%T Instruction set design issues relating to a static dataflow computer
%J Proceedings of the Ninth Annual International Symposium on Computer Architecture
%C Austin, Texas
%D April 1982
%O published as SIGARCH Computer Architecture News 10:3
%K isca isca9
%P 101-111

%A J.E. Smith
%T Decoupled access/execute computer architectures
%J Proceedings of the Ninth Annual International Symposium on Computer Architecture
%C Austin, Texas
%D April 1982
%O published as SIGARCH Computer Architecture News 10:3
%K isca isca9
%P 112-119

%A L.J. Caluwaerts
%A J. Debacker
%A J.A. Peperstraete
%T A dataflow architecture with a paged memory system
%J Proceedings of the Ninth Annual International Symposium on Computer Architecture
%C Austin, Texas
%D April 1982
%O published as SIGARCH Computer Architecture News 10:3
%K isca isca9
%P 120-127

%A B.R. Rau
%A C.D. Glaeser
%A R.L. Picard
%T Efficient code generation for horizontal architectures:
compiler techniques and architectural support
%J Proceedings of the Ninth Annual International Symposium on Computer Architecture
%C Austin, Texas
%D April 1982
%O published as SIGARCH Computer Architecture News 10:3
%K isca isca9
%P 131-139

%A G.C. Barton
%T Sentry: a novel hardware implementation
of classic operating system mechanisms
%J Proceedings of the Ninth Annual International Symposium on Computer Architecture
%C Austin, Texas
%D April 1982
%O published as SIGARCH Computer Architecture News 10:3
%K isca isca9
%P 140-147

%A M. Abramovici
%A Y.H. Levendel
%A P.R. Menon
%T A logic simulation machine
%J Proceedings of the Ninth Annual International Symposium on Computer Architecture
%C Austin, Texas
%D April 1982
%O published as SIGARCH Computer Architecture News 10:3
%K isca isca9
%P 148-157

%A S. Dasgupta
%A M. Olafsson
%T Towards a family of languages for the design and implementation
of machine architectures
%J Proceedings of the Ninth Annual International Symposium on Computer Architecture
%C Austin, Texas
%D April 1982
%O published as SIGARCH Computer Architecture News 10:3
%K isca isca9
%P 158-167

%A Y.H. Lee
%A K.G. Shin
%T Rollback propagation detection and performance evaluation
of FTMR2M - a fault-tolerant multiprocessor
%J Proceedings of the Ninth Annual International Symposium on Computer Architecture
%C Austin, Texas
%D April 1982
%O published as SIGARCH Computer Architecture News 10:3
%K isca isca9
%P 171-180

%A W. Lin
%A C. Wu
%T Design of a 2x2 fault-tolerant switching element
%J Proceedings of the Ninth Annual International Symposium on Computer Architecture
%C Austin, Texas
%D April 1982
%O published as SIGARCH Computer Architecture News 10:3
%K isca isca9
%P 181-189

%A D. Fussell
%A P. Varman
%T Fault-tolerant wafer-scale architecture for VLSI
%J Proceedings of the Ninth Annual International Symposium on Computer Architecture
%C Austin, Texas
%D April 1982
%O published as SIGARCH Computer Architecture News 10:3
%K isca isca9
%P 190-198

%A S. Pramanik
%T Database filters
%J Proceedings of the Ninth Annual International Symposium on Computer Architecture
%C Austin, Texas
%D April 1982
%O published as SIGARCH Computer Architecture News 10:3
%K isca isca9
%P 201-210

%A M. Tokoro
%A T. Takizuka
%T On the semantic structure of information
- a proposal of the abstract storage architecture
%J Proceedings of the Ninth Annual International Symposium on Computer Architecture
%C Austin, Texas
%D April 1982
%O published as SIGARCH Computer Architecture News 10:3
%K isca isca9
%P 211-217

%A Y. Dohi
%A A. Suzuki
%A N. Matsui
%T Hardware sorter and its application to data base machine
%J Proceedings of the Ninth Annual International Symposium on Computer Architecture
%C Austin, Texas
%D April 1982
%O published as SIGARCH Computer Architecture News 10:3
%K isca isca9
%P 218-225

%A P.C. Treleaven
%A R.P. Hopkins
%T Recursive computer architecture for VLSI
%J Proceedings of the Ninth Annual International Symposium on Computer Architecture
%C Austin, Texas
%D April 1982
%O published as SIGARCH Computer Architecture News 10:3
%K isca isca9
%P 229-238

%A M. Castan
%A E.I. Organick
%T u3L: an HLL-RISC processor for parallel execution
of FP-language programs
%J Proceedings of the Ninth Annual International Symposium on Computer Architecture
%C Austin, Texas
%D April 1982
%O published as SIGARCH Computer Architecture News 10:3
%K isca isca9
%P 239-247

%A F. Hommes
%T The heap/substitution concept - an implementation
of functional operations on data structures for a reduction machine
%J Proceedings of the Ninth Annual International Symposium on Computer Architecture
%C Austin, Texas
%D April 1982
%O published as SIGARCH Computer Architecture News 10:3
%K isca isca9
%P 248-256

%A P.F. Reynolds Jr
%T A shared resource algorithm for distributed simulation
%J Proceedings of the Ninth Annual International Symposium on Computer Architecture
%C Austin, Texas
%D April 1982
%O published as SIGARCH Computer Architecture News 10:3
%K isca isca9
%P 259-266

%A B.N. Jain
%T Duplication of packets and their detection
in X.25 communication protocols
%J Proceedings of the Ninth Annual International Symposium on Computer Architecture
%C Austin, Texas
%D April 1982
%O published as SIGARCH Computer Architecture News 10:3
%K isca isca9
%P 267-273

%A P. Markenscoff
%T A multiple processor system for real time control tasks
%J Proceedings of the Ninth Annual International Symposium on Computer Architecture
%C Austin, Texas
%D April 1982
%O published as SIGARCH Computer Architecture News 10:3
%K isca isca9
%P 274-280

%A L.J. Miller
%T A heterogeneous multiprocessor design
and the distributed scheduling of its task group workload
%J Proceedings of the Ninth Annual International Symposium on Computer Architecture
%C Austin, Texas
%D April 1982
%O published as SIGARCH Computer Architecture News 10:3
%K isca isca9
%P 283-290

%A G.H. Goble
%A M.H. Marsh
%T A dual processor VAX 11-780
%J Proceedings of the Ninth Annual International Symposium on Computer Architecture
%C Austin, Texas
%D April 1982
%O published as SIGARCH Computer Architecture News 10:3
%K isca isca9
%P 291-298

%A M. Dubois
%A F.A. Briggs
%T Effects of cache coherency in multiprocessors
%J Proceedings of the Ninth Annual International Symposium on Computer Architecture
%C Austin, Texas
%D April 1982
%O published as SIGARCH Computer Architecture News 10:3
%K isca isca9
%P 299-308c

%A T.N. Mudge
%A B.A. Makrucki
%T Probability analysis of a crossbar switch
%J Proceedings of the Ninth Annual International Symposium on Computer Architecture
%C Austin, Texas
%D April 1982
%O published as SIGARCH Computer Architecture News 10:3
%K isca isca9
%P 311-320

%A S.P. Levitan
%A C.C. Foster
%T Finding an extremum in a network
%J Proceedings of the Ninth Annual International Symposium on Computer Architecture
%C Austin, Texas
%D April 1982
%O published as SIGARCH Computer Architecture News 10:3
%K isca isca9
%P 321-325

%A U.V. Premkumer
%A J.C. Browne
%T Resource allocation in rectangular SW-Banyans
%J Proceedings of the Ninth Annual International Symposium on Computer Architecture
%C Austin, Texas
%D April 1982
%O published as SIGARCH Computer Architecture News 10:3
%K isca isca9
%P 326-333

%A M.V. Wilkes
%T Size, power and speed
%J Proceedings of the Tenth Annual International Symposium on Computer Architecture
%C Stockholm, Sweden
%D June 1983
%O published as SIGARCH Computer Architecture News 11:3
%K isca isca10
%P 2-4

%A W.K. Giloi
%T Towards a taxonomy of computer architecture
based on the machine data type view
%J Proceedings of the Tenth Annual International Symposium on Computer Architecture
%C Stockholm, Sweden
%D June 1983
%O published as SIGARCH Computer Architecture News 11:3
%K isca isca10
%P 6-15

%A A. Avizienis
%T Framework for a taxonomy of fault-tolerance attributes
in computer systems
%J Proceedings of the Tenth Annual International Symposium on Computer Architecture
%C Stockholm, Sweden
%D June 1983
%O published as SIGARCH Computer Architecture News 11:3
%K isca isca10
%P 16-21

%A B. Pehrson
%A J. Parrow
%T Caddie - an interactive design environment
%J Proceedings of the Tenth Annual International Symposium on Computer Architecture
%C Stockholm, Sweden
%D June 1983
%O published as SIGARCH Computer Architecture News 11:3
%K isca isca10
%P 24-31

%A S. Dasgupta
%T On the verification of computer architecture
using an architecture description language
%J Proceedings of the Tenth Annual International Symposium on Computer Architecture
%C Stockholm, Sweden
%D June 1983
%O published as SIGARCH Computer Architecture News 11:3
%K isca isca10
%P 32-38

%A R.M. King
%T Research on the synthesis of concurrent computing systems
%J Proceedings of the Tenth Annual International Symposium on Computer Architecture
%C Stockholm, Sweden
%D June 1983
%O published as SIGARCH Computer Architecture News 11:3
%K isca isca10
%P 39-46

%A A.L. Fisher
%A H.T. Kung
%A L.M. Monier
%A Y. Dohi
%T Architecture of the PSC: a programmable systolic chip
%J Proceedings of the Tenth Annual International Symposium on Computer Architecture
%C Stockholm, Sweden
%D June 1983
%O published as SIGARCH Computer Architecture News 11:3
%K isca isca10
%P 48-53

%A A.L. Fisher
%A H.T. Kung
%T Synchronizing large VLSI processor arrays
%J Proceedings of the Tenth Annual International Symposium on Computer Architecture
%C Stockholm, Sweden
%D June 1983
%O published as SIGARCH Computer Architecture News 11:3
%K isca isca10
%P 54-58

%A R.A. Wagner
%T The boolean vector machine (BVM)
%J Proceedings of the Tenth Annual International Symposium on Computer Architecture
%C Stockholm, Sweden
%D June 1983
%O published as SIGARCH Computer Architecture News 11:3
%K isca isca10
%P 59-66

%A M.A. Bonuccelli
%A E. Lodi
%A F. Luccio
%A P. Maestrini
%A L. Pagli
%T A VLSI area machine for relational data bases
%J Proceedings of the Tenth Annual International Symposium on Computer Architecture
%C Stockholm, Sweden
%D June 1983
%O published as SIGARCH Computer Architecture News 11:3
%K isca isca10
%P 67-73

%A L.J. Caluwaerts
%A J. DeBacker
%A J. Peperstraete
%T Implementing streams on a data flow computer system with paged memory
%J Proceedings of the Tenth Annual International Symposium on Computer Architecture
%C Stockholm, Sweden
%D June 1983
%O published as SIGARCH Computer Architecture News 11:3
%K isca isca10
%P 76-83

%A J.E. Requa
%T The piecewise data flow architecture:
control flow and register management
%J Proceedings of the Tenth Annual International Symposium on Computer Architecture
%C Stockholm, Sweden
%D June 1983
%O published as SIGARCH Computer Architecture News 11:3
%K isca isca10
%P 84-89

%A M. Tokoro
%A J.R. Jagannathan
%A H. Sunahara
%T On the working set concept for data-flow machines
%J Proceedings of the Tenth Annual International Symposium on Computer Architecture
%C Stockholm, Sweden
%D June 1983
%O published as SIGARCH Computer Architecture News 11:3
%K isca isca10
%P 90-97

%A R.W. Marczynski
%A J. Milewski
%T A data driven system based on a microprogrammed processor module
%J Proceedings of the Tenth Annual International Symposium on Computer Architecture
%C Stockholm, Sweden
%D June 1983
%O published as SIGARCH Computer Architecture News 11:3
%K isca isca10
%P 98-106

%A D.A. Patterson
%A P. Garrison
%A M. Hill
%A D. Lioupis
%A C. Nyberg
%A T. Sippel
%A K. VanDyke
%T Architecture of a VLSI instruction cache for a RISC
%J Proceedings of the Tenth Annual International Symposium on Computer Architecture
%C Stockholm, Sweden
%D June 1983
%O published as SIGARCH Computer Architecture News 11:3
%K isca isca10
%P 108-116

%A P.C.C. Yeh
%A J.H. Patel
%A E.S. Davidson
%T Performance of shared cache for parallel-pipelined computer systems
%J Proceedings of the Tenth Annual International Symposium on Computer Architecture
%C Stockholm, Sweden
%D June 1983
%O published as SIGARCH Computer Architecture News 11:3
%K isca isca10
%P 117-123

%A J.R. Goodman
%T Using cache memory to reduce processor-memory traffic
%J Proceedings of the Tenth Annual International Symposium on Computer Architecture
%C Stockholm, Sweden
%D June 1983
%O published as SIGARCH Computer Architecture News 11:3
%K isca isca10
%P 124-131

%A J.E. Smith
%A J.R. Goodman
%T A study of instruction cache organizations and replacement policies
%J Proceedings of the Tenth Annual International Symposium on Computer Architecture
%C Stockholm, Sweden
%D June 1983
%O published as SIGARCH Computer Architecture News 11:3
%K isca isca10
%P 132-137

%A J.A. Fisher
%T Very long instruction word architectures and the ELI-512
%J Proceedings of the Tenth Annual International Symposium on Computer Architecture
%C Stockholm, Sweden
%D June 1983
%O published as SIGARCH Computer Architecture News 11:3
%K isca isca10
%P 140-150
%K VLIW

%A S. Tomita
%A K. Shibayama
%A T. Kitamura
%A T. Nakata
%A H. Hagiwara
%T A user-microprogrammable, local host computer
with low-level parallelism
%J Proceedings of the Tenth Annual International Symposium on Computer Architecture
%C Stockholm, Sweden
%D June 1983
%O published as SIGARCH Computer Architecture News 11:3
%K isca isca10
%P 151-157

%A R.H. Gumphertz
%T Combining tags with error codes
%J Proceedings of the Tenth Annual International Symposium on Computer Architecture
%C Stockholm, Sweden
%D June 1983
%O published as SIGARCH Computer Architecture News 11:3
%K isca isca10
%P 160-165

%A Y.G. Park
%A J.W. Cho
%T Fault diagnosis of bit-slice processor
%J Proceedings of the Tenth Annual International Symposium on Computer Architecture
%C Stockholm, Sweden
%D June 1983
%O published as SIGARCH Computer Architecture News 11:3
%K isca isca10
%P 166-172

%A M.A. Fiol
%A I. Alegre
%A J.L.A. Yebra
%T Line digraph iterations and the (d,k) problem for directed graphs
%J Proceedings of the Tenth Annual International Symposium on Computer Architecture
%C Stockholm, Sweden
%D June 1983
%O published as SIGARCH Computer Architecture News 11:3
%K isca isca10
%P 174-177

%A E. Opper
%A M. Malek
%A G.J. Lipovski
%T Resource allocation in rectangular CC-Banyans
%J Proceedings of the Tenth Annual International Symposium on Computer Architecture
%C Stockholm, Sweden
%D June 1983
%O published as SIGARCH Computer Architecture News 11:3
%K isca isca10
%P 178-184

%A F. Sovis
%T Uniform theory of the shuffle-exchange type permutation networks
%J Proceedings of the Tenth Annual International Symposium on Computer Architecture
%C Stockholm, Sweden
%D June 1983
%O published as SIGARCH Computer Architecture News 11:3
%K isca isca10
%P 185-192

%A V.P. Srini
%A J.F. Asenjo
%T Analysis of Cray-1S architecture
%J Proceedings of the Tenth Annual International Symposium on Computer Architecture
%C Stockholm, Sweden
%D June 1983
%O published as SIGARCH Computer Architecture News 11:3
%K isca isca10
%P 194-206

%A H.F. Jordan
%T Performance measurements on HEP - a pipelined MIMD computer
%J Proceedings of the Tenth Annual International Symposium on Computer Architecture
%C Stockholm, Sweden
%D June 1983
%O published as SIGARCH Computer Architecture News 11:3
%K isca isca10
%P 207-212

%A H. Amano
%A T. Yoshida
%A H. Aiso
%T (SM)2: sparse matrix solving machine
%J Proceedings of the Tenth Annual International Symposium on Computer Architecture
%C Stockholm, Sweden
%D June 1983
%O published as SIGARCH Computer Architecture News 11:3
%K isca isca10
%P 213-220

%A R.K. Krishnan
%A A.K. Rajasekar
%A C.S. Moghe
%T An experimental system for computer science instruction
%J Proceedings of the Tenth Annual International Symposium on Computer Architecture
%C Stockholm, Sweden
%D June 1983
%O published as SIGARCH Computer Architecture News 11:3
%K isca isca10
%P 222-227

%A K. Kronlof
%T Execution control and memory management
of a data flow signal processor
%J Proceedings of the Tenth Annual International Symposium on Computer Architecture
%C Stockholm, Sweden
%D June 1983
%O published as SIGARCH Computer Architecture News 11:3
%K isca isca10
%P 230-235

%A M. Kishi
%A H. Yasuhara
%A Y. Kawamura
%T DDDP: a distributed data driven processor
%J Proceedings of the Tenth Annual International Symposium on Computer Architecture
%C Stockholm, Sweden
%D June 1983
%O published as SIGARCH Computer Architecture News 11:3
%K isca isca10
%P 236-242

%A N. Takahashi
%A M. Amamiya
%T A data flow processor array system: design and analysis
%J Proceedings of the Tenth Annual International Symposium on Computer Architecture
%C Stockholm, Sweden
%D June 1983
%O published as SIGARCH Computer Architecture News 11:3
%K isca isca10
%P 243-250

%A K.A. Pier
%T A retrospective on the Dorado: a high-performance personal computer
%J Proceedings of the Tenth Annual International Symposium on Computer Architecture
%C Stockholm, Sweden
%D June 1983
%O published as SIGARCH Computer Architecture News 11:3
%K isca isca10
%P 252-269

%A R.J. Dugan
%T System/370 extended architecture:
a program view of the channel subsystem
%J Proceedings of the Tenth Annual International Symposium on Computer Architecture
%C Stockholm, Sweden
%D June 1983
%O published as SIGARCH Computer Architecture News 11:3
%K isca isca10
%P 270-276

%A R.L. Norton
%A J.A. Abraham
%T Adaptive interpretation as a means of
exploiting complex instruction sets
%J Proceedings of the Tenth Annual International Symposium on Computer Architecture
%C Stockholm, Sweden
%D June 1983
%O published as SIGARCH Computer Architecture News 11:3
%K isca isca10
%P 277-282

%A M. Kumar
%A D.M. Dias
%A J.R. Jump
%T Switching strategies in a class of packet switching networks
%J Proceedings of the Tenth Annual International Symposium on Computer Architecture
%C Stockholm, Sweden
%D June 1983
%O published as SIGARCH Computer Architecture News 11:3
%K isca isca10
%P 284-300

%A B.W. Wah
%T A comparative study of distributed resource sharing
on multiprocessors
%J Proceedings of the Tenth Annual International Symposium on Computer Architecture
%C Stockholm, Sweden
%D June 1983
%O published as SIGARCH Computer Architecture News 11:3
%K isca isca10
%P 301-308

%A W.K. Fuchs
%A J.A. Abraham
%A K.-H. Huang
%T Concurrent error detection in VLSI interconnection networks
%J Proceedings of the Tenth Annual International Symposium on Computer Architecture
%C Stockholm, Sweden
%D June 1983
%O published as SIGARCH Computer Architecture News 11:3
%K isca isca10
%P 309-315

%A W.K. Giloi
%A P. Behr
%T Hierarchical function distribution
- a design principle for advanced multicomputer architectures
%J Proceedings of the Tenth Annual International Symposium on Computer Architecture
%C Stockholm, Sweden
%D June 1983
%O published as SIGARCH Computer Architecture News 11:3
%K isca isca10
%P 318-325

%A L. Stringa
%T EMMA: an industrial experience on large multiprocessing architectures
%J Proceedings of the Tenth Annual International Symposium on Computer Architecture
%C Stockholm, Sweden
%D June 1983
%O published as SIGARCH Computer Architecture News 11:3
%K isca isca10
%P 326-333

%A L. Philipson
%A B. Nilsson
%A B. Breidegard
%T A communication structure for a multiprocessor computer
with distributed global memory
%J Proceedings of the Tenth Annual International Symposium on Computer Architecture
%C Stockholm, Sweden
%D June 1983
%O published as SIGARCH Computer Architecture News 11:3
%K isca isca10
%P 334-340

%A H. Hayashi
%A A. Hattori
%A H. Akimoto
%T ALPHA: a high-performance LISP machine equipped with
a new stack structure and garbage collection system
%J Proceedings of the Tenth Annual International Symposium on Computer Architecture
%C Stockholm, Sweden
%D June 1983
%O published as SIGARCH Computer Architecture News 11:3
%K isca isca10
%P 342-348

%A S. Umeyama
%A K. Tamura
%T A parallel execution model of logic programs
%J Proceedings of the Tenth Annual International Symposium on Computer Architecture
%C Stockholm, Sweden
%D June 1983
%O published as SIGARCH Computer Architecture News 11:3
%K isca isca10
%P 349-355

%A C. Schmittgen
%A W. Kluge
%T A system architecture for the concurrent evaluation
of applicative program expressions
%J Proceedings of the Tenth Annual International Symposium on Computer Architecture
%C Stockholm, Sweden
%D June 1983
%O published as SIGARCH Computer Architecture News 11:3
%K isca isca10
%P 356-362

%A Y. Yamaguchi
%A K. Toda
%A T. Yuba
%T A performance evaluation of a Lisp-based data-driven machine (EM3)
%J Proceedings of the Tenth Annual International Symposium on Computer Architecture
%C Stockholm, Sweden
%D June 1983
%O published as SIGARCH Computer Architecture News 11:3
%K isca isca10
%P 363-369

%A S.L. Tanimoto
%T A pyramidal approach to parallel processing
%J Proceedings of the Tenth Annual International Symposium on Computer Architecture
%C Stockholm, Sweden
%D June 1983
%O published as SIGARCH Computer Architecture News 11:3
%K isca isca10
%P 372-378

%A G. Gaillat
%T The design of a parallel processor for image processing
on-board satellites: an application oriented approach
%J Proceedings of the Tenth Annual International Symposium on Computer Architecture
%C Stockholm, Sweden
%D June 1983
%O published as SIGARCH Computer Architecture News 11:3
%K isca isca10
%P 379-386

%A H. Nishimura
%A H. Ohno
%A T. Kawata
%A I. Shirakawa
%A K. Omura
%T LINKS-1: a parallel pipelined multimicrocomputer system
for image creation
%J Proceedings of the Tenth Annual International Symposium on Computer Architecture
%C Stockholm, Sweden
%D June 1983
%O published as SIGARCH Computer Architecture News 11:3
%K isca isca10
%P 387-394

%A T. Ericsson
%A P.E. Danielsson
%T LIPP - A SIMD multiprocessor architecture for image processing
%J Proceedings of the Tenth Annual International Symposium on Computer Architecture
%C Stockholm, Sweden
%D June 1983
%O published as SIGARCH Computer Architecture News 11:3
%K isca isca10
%P 395-400

%A P.C. Treleaven
%T The new generation of computer architecture
%J Proceedings of the Tenth Annual International Symposium on Computer Architecture
%C Stockholm, Sweden
%D June 1983
%O published as SIGARCH Computer Architecture News 11:3
%K isca isca10
%P 402-409

%A S. Uchida
%T Inference machine
%J Proceedings of the Tenth Annual International Symposium on Computer Architecture
%C Stockholm, Sweden
%D June 1983
%O published as SIGARCH Computer Architecture News 11:3
%K isca isca10
%P 410-416

%A M.-O. Tohru
%T Overview of the fifth generation computer system project
%J Proceedings of the Tenth Annual International Symposium on Computer Architecture
%C Stockholm, Sweden
%D June 1983
%O published as SIGARCH Computer Architecture News 11:3
%K isca isca10
%P 417-422

%A K. Murikami
%A T. Kakuta
%A N. Miyazaki
%A S. Shibayama
%A H. Yokota
%T A relational data base machine: first step to knowledge base machine
%J Proceedings of the Tenth Annual International Symposium on Computer Architecture
%C Stockholm, Sweden
%D June 1983
%O published as SIGARCH Computer Architecture News 11:3
%K isca isca10
%P 423-425

%A Arvind
%A R.A. Iannucci
%T A critique of multiprocessing von Neumann style
%J Proceedings of the Tenth Annual International Symposium on Computer Architecture
%C Stockholm, Sweden
%D June 1983
%O published as SIGARCH Computer Architecture News 11:3
%K isca isca10
%P 426-436

%A F.J. Burkowski
%T A vector and array multiprocessor extension
of the Sylvan architecture
%J Proceedings of the Eleventh Annual International Symposium on Computer Architecture
%C Ann Arbor, Michigan
%D June 1984
%O published as SIGARCH Computer Architecture News 12:3
%K isca isca11
%P 4-11

%A A. Kapauan
%A J.T. Field
%A D.B. Gannon
%A L. Snyder
%T The Pringle parallel computer
%J Proceedings of the Eleventh Annual International Symposium on Computer Architecture
%C Ann Arbor, Michigan
%D June 1984
%O published as SIGARCH Computer Architecture News 12:3
%K isca isca11
%P 12-20

%A M. Yasrebi
%A G.J. Lipovski
%T A state-of-the-art SIMD two-dimensional FFT array processor
%J Proceedings of the Eleventh Annual International Symposium on Computer Architecture
%C Ann Arbor, Michigan
%D June 1984
%O published as SIGARCH Computer Architecture News 12:3
%K isca isca11
%P 21-27

%A Y.-W. Ma
%A R. Krishnamurti
%T The architecture of Replica - a special purpose computer system
for active multi-sensory perception of 3-dimensional objects
%J Proceedings of the Eleventh Annual International Symposium on Computer Architecture
%C Ann Arbor, Michigan
%D June 1984
%O published as SIGARCH Computer Architecture News 12:3
%K isca isca11
%P 30-37

%A S.M. Goldwasser
%T A generalized object display processor architecture
%J Proceedings of the Eleventh Annual International Symposium on Computer Architecture
%C Ann Arbor, Michigan
%D June 1984
%O published as SIGARCH Computer Architecture News 12:3
%K isca isca11
%P 38-47

%A K. Kawakami
%A S. Shimazaki
%T A special purpose LSI processor using the DDA algorithm
for image transformation
%J Proceedings of the Eleventh Annual International Symposium on Computer Architecture
%C Ann Arbor, Michigan
%D June 1984
%O published as SIGARCH Computer Architecture News 12:3
%K isca isca11
%P 48-54

%A B.W. Wah
%A G.-J. Li
%A C.-F. Yu
%T The status of MANIP: a multicomputer architecture
for solving combinatorial extremum problems
%J Proceedings of the Eleventh Annual International Symposium on Computer Architecture
%C Ann Arbor, Michigan
%D June 1984
%O published as SIGARCH Computer Architecture News 12:3
%K isca isca11
%P 56-63

%A R. Gonzalez-Rubio
%A J. Rohmer
%A D. Terral
%T The Schuss filter: a processor for non-numerical data processing
%J Proceedings of the Eleventh Annual International Symposium on Computer Architecture
%C Ann Arbor, Michigan
%D June 1984
%O published as SIGARCH Computer Architecture News 12:3
%K isca isca11
%P 64-73

%A C. Ebeling
%A A. Palay
%T The design and implementation of a VLSI chess move generator
%J Proceedings of the Eleventh Annual International Symposium on Computer Architecture
%C Ann Arbor, Michigan
%D June 1984
%O published as SIGARCH Computer Architecture News 12:3
%K isca isca11
%P 74-80

%A M. Lee
%A C.-L. Wu
%T Performance analysis of circuit switching
baseline interconnection networks
%J Proceedings of the Eleventh Annual International Symposium on Computer Architecture
%C Ann Arbor, Michigan
%D June 1984
%O published as SIGARCH Computer Architecture News 12:3
%K isca isca11
%P 82-90

%A C.P. Kruskal
%A M. Snir
%T On the importance of being square
%J Proceedings of the Eleventh Annual International Symposium on Computer Architecture
%C Ann Arbor, Michigan
%D June 1984
%O published as SIGARCH Computer Architecture News 12:3
%K isca isca11
%P 91-98

%A C.-Y. Chin
%A K. Hwang
%T Connection principles for multipath packet switching networks
%J Proceedings of the Eleventh Annual International Symposium on Computer Architecture
%C Ann Arbor, Michigan
%D June 1984
%O published as SIGARCH Computer Architecture News 12:3
%K isca isca11
%P 99-108

%A S. Weiss
%A J.E. Smith
%T Instruction issue logic for pipelined supercomputers
%J Proceedings of the Eleventh Annual International Symposium on Computer Architecture
%C Ann Arbor, Michigan
%D June 1984
%O published as SIGARCH Computer Architecture News 12:3
%K isca isca11
%P 110-118

%A R.G. Wedig
%A M.A. Rose
%T The reduction of branch instruction execution overhead
using structured control flow
%J Proceedings of the Eleventh Annual International Symposium on Computer Architecture
%C Ann Arbor, Michigan
%D June 1984
%O published as SIGARCH Computer Architecture News 12:3
%K isca isca11
%P 119-125

%A U. Bannerjee
%A D.D. Gajski
%T Fast execution of loops with IF statements
%J Proceedings of the Eleventh Annual International Symposium on Computer Architecture
%C Ann Arbor, Michigan
%D June 1984
%O published as SIGARCH Computer Architecture News 12:3
%K isca isca11
%P 126-132

%A D.D. Gajski
%A W. Kim
%A S. Fushimi
%T A parallel pipelined relational query processor:
and architectural overview
%J Proceedings of the Eleventh Annual International Symposium on Computer Architecture
%C Ann Arbor, Michigan
%D June 1984
%O published as SIGARCH Computer Architecture News 12:3
%K isca isca11
%P 134-141

%A A.K. Somani
%A V.K. Agrawal
%T An efficient VLSI dictionary machine
%J Proceedings of the Eleventh Annual International Symposium on Computer Architecture
%C Ann Arbor, Michigan
%D June 1984
%O published as SIGARCH Computer Architecture News 12:3
%K isca isca11
%P 142-150

%A A.L. Fisher
%T Dictionary machines with a small number of processors
%J Proceedings of the Eleventh Annual International Symposium on Computer Architecture
%C Ann Arbor, Michigan
%D June 1984
%O published as SIGARCH Computer Architecture News 12:3
%K isca isca11
%P 151-156

%A M.D. Hill
%A A.J. Smith
%T Experimental evaluation of on-chip multiprocessor cache memories
%J Proceedings of the Eleventh Annual International Symposium on Computer Architecture
%C Ann Arbor, Michigan
%D June 1984
%O published as SIGARCH Computer Architecture News 12:3
%K isca isca11
%P 158-166

%A J.R. Goodman
%A M.-C. Chiang
%T The use of static column RAM as a memory hierarchy
%J Proceedings of the Eleventh Annual International Symposium on Computer Architecture
%C Ann Arbor, Michigan
%D June 1984
%O published as SIGARCH Computer Architecture News 12:3
%K isca isca11
%P 167-174

%A Y. Ishikawa
%A M. Tokoro
%T The design of an object oriented architecture
%J Proceedings of the Eleventh Annual International Symposium on Computer Architecture
%C Ann Arbor, Michigan
%D June 1984
%O published as SIGARCH Computer Architecture News 12:3
%K isca isca11
%P 178-187

%A D. Ungar
%A R. Blau
%A P. Foley
%A D. Samples
%A D.A. Patterson
%T Architecture of SOAR: Smalltalk on a RISC
%J Proceedings of the Eleventh Annual International Symposium on Computer Architecture
%C Ann Arbor, Michigan
%D June 1984
%O published as SIGARCH Computer Architecture News 12:3
%K isca isca11
%P 188-197

%A P. Bose
%A E.S. Davidson
%T Design of instruction set architectures
for support of high-level languages
%J Proceedings of the Eleventh Annual International Symposium on Computer Architecture
%C Ann Arbor, Michigan
%D June 1984
%O published as SIGARCH Computer Architecture News 12:3
%K isca isca11
%P 198-206

%A P. Quinton
%T Automatic synthesis of systolic arrays
from uniform recurrent equations
%J Proceedings of the Eleventh Annual International Symposium on Computer Architecture
%C Ann Arbor, Michigan
%D June 1984
%O published as SIGARCH Computer Architecture News 12:3
%K isca isca11
%P 208-214

%A C.N. Chang
%A D.Y.Y. Yun
%T Multi-dimensional systolic networks for discrete Fourier transform
%J Proceedings of the Eleventh Annual International Symposium on Computer Architecture
%C Ann Arbor, Michigan
%D June 1984
%O published as SIGARCH Computer Architecture News 12:3
%K isca isca11
%P 215-222

%A J.A.B. Fortes
%A D.I. Moldovan
%T Data broadcasting in linearly scheduled array processors
%J Proceedings of the Eleventh Annual International Symposium on Computer Architecture
%C Ann Arbor, Michigan
%D June 1984
%O published as SIGARCH Computer Architecture News 12:3
%K isca isca11
%P 223-231

%A I.V. Ramakrishnan
%A P.J. Varman
%T Modular matrix multiplication on a linear array
%J Proceedings of the Eleventh Annual International Symposium on Computer Architecture
%C Ann Arbor, Michigan
%D June 1984
%O published as SIGARCH Computer Architecture News 12:3
%K isca isca11
%P 232-238

%A T.R.N. Rao
%T Joint encryption and error correction schemes
%J Proceedings of the Eleventh Annual International Symposium on Computer Architecture
%C Ann Arbor, Michigan
%D June 1984
%O published as SIGARCH Computer Architecture News 12:3
%K isca isca11
%P 240-241

%A B. Bose
%T Unidirectional error correction/detection for VLSI memory
%J Proceedings of the Eleventh Annual International Symposium on Computer Architecture
%C Ann Arbor, Michigan
%D June 1984
%O published as SIGARCH Computer Architecture News 12:3
%K isca isca11
%P 242-244

%A C.L. Chen
%T Error-correcting codes for semiconductor memories
%J Proceedings of the Eleventh Annual International Symposium on Computer Architecture
%C Ann Arbor, Michigan
%D June 1984
%O published as SIGARCH Computer Architecture News 12:3
%K isca isca11
%P 245-247

%A K. Abdel-Ghaffar
%A R.J. McEliece
%T Soft error correction for increased densities in VLSI memories
%J Proceedings of the Eleventh Annual International Symposium on Computer Architecture
%C Ann Arbor, Michigan
%D June 1984
%O published as SIGARCH Computer Architecture News 12:3
%K isca isca11
%P 248-250

%A R.M. King
%A R.A. Wagner
%T Combining speed with alpha-particle induced memory error tolerance
in a large boolean vector machine
%J Proceedings of the Eleventh Annual International Symposium on Computer Architecture
%C Ann Arbor, Michigan
%D June 1984
%O published as SIGARCH Computer Architecture News 12:3
%K isca isca11
%P 251-253
%O extended abstract

%A L.N. Bhuyan
%T On the performance of loosely coupled multiprocessors
%J Proceedings of the Eleventh Annual International Symposium on Computer Architecture
%C Ann Arbor, Michigan
%D June 1984
%O published as SIGARCH Computer Architecture News 12:3
%K isca isca11
%P 256-262

%A R. Methotra
%A S.N. Talukdar
%T Scheduling of tasks for distributed processors
%J Proceedings of the Eleventh Annual International Symposium on Computer Architecture
%C Ann Arbor, Michigan
%D June 1984
%O published as SIGARCH Computer Architecture News 12:3
%K isca isca11
%P 263-270

%A K.M. Kavi
%A E.W. Banios
%A B.D. Shriver
%T Message repository definitional facility:
and architectural model for interprocess communication
%J Proceedings of the Eleventh Annual International Symposium on Computer Architecture
%C Ann Arbor, Michigan
%D June 1984
%O published as SIGARCH Computer Architecture News 12:3
%K isca isca11
%P 271-278

%A P. Bannerjee
%A J.A. Abraham
%T Fault-secure algorithms for multiple-processor systems
%J Proceedings of the Eleventh Annual International Symposium on Computer Architecture
%C Ann Arbor, Michigan
%D June 1984
%O published as SIGARCH Computer Architecture News 12:3
%K isca isca11
%P 279-287

%A L. Bic
%T Execution of logic programs on a dataflow architecture
%J Proceedings of the Eleventh Annual International Symposium on Computer Architecture
%C Ann Arbor, Michigan
%D June 1984
%O published as SIGARCH Computer Architecture News 12:3
%K isca isca11
%P 290-296

%A W.G. Rudd
%A D.A. Buell
%A D.M. Chiarulli
%T A high performance factoring machine
%J Proceedings of the Eleventh Annual International Symposium on Computer Architecture
%C Ann Arbor, Michigan
%D June 1984
%O published as SIGARCH Computer Architecture News 12:3
%K isca isca11
%P 297-300

%A J.S. Emer
%A D.W. Clark
%T A characterization of processor performance in the VAX 11-780
%J Proceedings of the Eleventh Annual International Symposium on Computer Architecture
%C Ann Arbor, Michigan
%D June 1984
%O published as SIGARCH Computer Architecture News 12:3
%K isca isca11
%P 301-310

%A W.D. Moeller
%A G. Sandweg
%T The peripheral processor PP4: a highly VLSI processor
%J Proceedings of the Eleventh Annual International Symposium on Computer Architecture
%C Ann Arbor, Michigan
%D June 1984
%O published as SIGARCH Computer Architecture News 12:3
%K isca isca11
%P 312-318

%A L. Philipson
%T VLSI based design principles for MIMD multiprocessor computers
with distributed memory management
%J Proceedings of the Eleventh Annual International Symposium on Computer Architecture
%C Ann Arbor, Michigan
%D June 1984
%O published as SIGARCH Computer Architecture News 12:3
%K isca isca11
%P 319-327

%A M.R. Samatham
%A D.K. Pradhan
%T A multiprocessor network suitable for single-chip VLSI implementation
%J Proceedings of the Eleventh Annual International Symposium on Computer Architecture
%C Ann Arbor, Michigan
%D June 1984
%O published as SIGARCH Computer Architecture News 12:3
%K isca isca11
%P 328-337

%A L. Rudolph
%A Z. Segall
%T Dynamic decentralized cache schemes for MIMD parallel processors
%J Proceedings of the Eleventh Annual International Symposium on Computer Architecture
%C Ann Arbor, Michigan
%D June 1984
%O published as SIGARCH Computer Architecture News 12:3
%K isca isca11
%P 340-347

%A M.S. Papamarcos
%A J.H. Patel
%T A low-overhead coherence solution for multiprocessors
with private cache memories
%J Proceedings of the Eleventh Annual International Symposium on Computer Architecture
%C Ann Arbor, Michigan
%D June 1984
%O published as SIGARCH Computer Architecture News 12:3
%K isca isca11
%P 348-354

%A J. Archibald
%A J.-L. Baer
%T An economical solution to the cache coherence problem
%J Proceedings of the Eleventh Annual International Symposium on Computer Architecture
%C Ann Arbor, Michigan
%D June 1984
%O published as SIGARCH Computer Architecture News 12:3
%K isca isca11
%P 355-362

%A I.J. Haikala
%T Cache hit ratios with geometric task switch intervals
%J Proceedings of the Eleventh Annual International Symposium on Computer Architecture
%C Ann Arbor, Michigan
%D June 1984
%O published as SIGARCH Computer Architecture News 12:3
%K isca isca11
%P 364-372

%A V.K. Prasanna Kumar
%A C.S. Raghavendra
%T Array processor with multiple broadcasting
%J Proceedings of the Twelfth Annual International Symposium on Computer Architecture
%C Boston, Massachusetts
%D June 1985
%O published as SIGARCH Computer Architecture News 13:3
%K isca isca12
%P 2-10
%K simd

%A G. Wolf
%A J.R. Jump
%T Matrix multiplication in an interleaved array processing architecture
%J Proceedings of the Twelfth Annual International Symposium on Computer Architecture
%C Boston, Massachusetts
%D June 1985
%O published as SIGARCH Computer Architecture News 13:3
%K isca isca12
%P 11-17
%K simd

%A J.R. Goodman
%A J.-t. Hsieh
%A K. Liou
%A A.R. Pleszkun
%A P.B. Schechter
%A H.C. Young
%T PIPE: a VLSI decoupled architecture
%J Proceedings of the Twelfth Annual International Symposium on Computer Architecture
%C Boston, Massachusetts
%D June 1985
%O published as SIGARCH Computer Architecture News 13:3
%K isca isca12
%P 20-27

%A P.Y.T. Hsu
%A J.T. Rahmeh
%A E.S. Davidson
%A J.A. Abraham
%T TIDBITS: speedup via time-delay bit-slicing
in ALU design for VLSI technology
%J Proceedings of the Twelfth Annual International Symposium on Computer Architecture
%C Boston, Massachusetts
%D June 1985
%O published as SIGARCH Computer Architecture News 13:3
%K isca isca12
%P 28-35
%K pipe

%A J.E. Smith
%A A.R. Pleszkun
%T Implementation of precise interrupts in pipelined processors
%J Proceedings of the Twelfth Annual International Symposium on Computer Architecture
%C Boston, Massachusetts
%D June 1985
%O published as SIGARCH Computer Architecture News 13:3
%K isca isca12
%P 36-44
%K pipe

%A M. Hasegawa
%A Y. Shigei
%T High-speed top-of-stack scheme for VLSI processor:
a management algorithm and its analysis
%J Proceedings of the Twelfth Annual International Symposium on Computer Architecture
%C Boston, Massachusetts
%D June 1985
%O published as SIGARCH Computer Architecture News 13:3
%K isca isca12
%P 48-54
%K store

%A C.Y. Hitchcock,\ III
%A H.M. Brinkley
%T Analyzing multiple register sets
%J Proceedings of the Twelfth Annual International Symposium on Computer Architecture
%C Boston, Massachusetts
%D June 1985
%O published as SIGARCH Computer Architecture News 13:3
%K isca isca12
%P 55-63
%K store

%A A.J. Smith
%T Cache evaluation and the impact of workload choice
%J Proceedings of the Twelfth Annual International Symposium on Computer Architecture
%C Boston, Massachusetts
%D June 1985
%O published as SIGARCH Computer Architecture News 13:3
%K isca isca12
%P 64-73

%A D.A. Moon
%T Architecture of the Symbolics 3600
%J Proceedings of the Twelfth Annual International Symposium on Computer Architecture
%C Boston, Massachusetts
%D June 1985
%O published as SIGARCH Computer Architecture News 13:3
%K isca isca12
%P 76-83
%K lisp

%A A. Ram
%A J.H. Patel
%T Parallel garbage collection without synchronization overhead
%J Proceedings of the Twelfth Annual International Symposium on Computer Architecture
%C Boston, Massachusetts
%D June 1985
%O published as SIGARCH Computer Architecture News 13:3
%K isca isca12
%P 84-90
%K store

%A G.S. Sohi
%A E.S. Davidson
%A J.H. Patel
%T An efficient LISP-execution architecture
with a new representation for list structures
%J Proceedings of the Twelfth Annual International Symposium on Computer Architecture
%C Boston, Massachusetts
%D June 1985
%O published as SIGARCH Computer Architecture News 13:3
%K isca isca12
%P 91-98
%K lisp store

%A H. Amano
%A T. Boku
%A T. Kudoh
%A H. Aiso
%T (SM)2-II: a new version of the sparse matrix solving machine
%J Proceedings of the Twelfth Annual International Symposium on Computer Architecture
%C Boston, Massachusetts
%D June 1985
%O published as SIGARCH Computer Architecture News 13:3
%K isca isca12
%P 100-107
%K mimd

%A J. Beetem
%A M. Denneau
%A D. Weingarten
%T The GF11 supercomputer
%J Proceedings of the Twelfth Annual International Symposium on Computer Architecture
%C Boston, Massachusetts
%D June 1985
%O published as SIGARCH Computer Architecture News 13:3
%K isca isca12
%P 108-115
%K simd super

%A B.W. Smith
%A H.J. Siegel
%T Models for use in the design of macro-pipelined parallel processors
%J Proceedings of the Twelfth Annual International Symposium on Computer Architecture
%C Boston, Massachusetts
%D June 1985
%O published as SIGARCH Computer Architecture News 13:3
%K isca isca12
%P 116-123

%A J. Edler
%A A. Gottlieb
%A C.P. Kruskal
%A K.P. McAuliffe
%A L. Rudolph
%A M. Snir
%A P.J. Teller
%A J. Wilson
%T Issues related to MIMD shared-memory computers:
the NYU ultracomputer approach
%J Proceedings of the Twelfth Annual International Symposium on Computer Architecture
%C Boston, Massachusetts
%D June 1985
%O published as SIGARCH Computer Architecture News 13:3
%K isca isca12
%P 126-135

%A R.N. Ibbett
%A P.C. Capon
%A N.P. Topham
%T MU6V: a parallel vector processing system
%J Proceedings of the Twelfth Annual International Symposium on Computer Architecture
%C Boston, Massachusetts
%D June 1985
%O published as SIGARCH Computer Architecture News 13:3
%K isca isca12
%P 136-144

%A S.F. Lundstrom
%T A decentralized control, highly concurrent multiprocessor
%J Proceedings of the Twelfth Annual International Symposium on Computer Architecture
%C Boston, Massachusetts
%D June 1985
%O published as SIGARCH Computer Architecture News 13:3
%K isca isca12
%P 145-151

%A W.J. Dally
%A J.T. Kajiya
%T An object oriented architecture
%J Proceedings of the Twelfth Annual International Symposium on Computer Architecture
%C Boston, Massachusetts
%D June 1985
%O published as SIGARCH Computer Architecture News 13:3
%K isca isca12
%P 154-161

%A E.F. Gehringer
%A J.L. Keedy
%T Tagged architecture: how compelling are its advantages ?
%J Proceedings of the Twelfth Annual International Symposium on Computer Architecture
%C Boston, Massachusetts
%D June 1985
%O published as SIGARCH Computer Architecture News 13:3
%K isca isca12
%P 162-170

%A S. Nanba
%A N. Ohno
%A H. Kubo
%A H. Morisue
%A T. Ohshima
%A H. Yamagishi
%T VM/4: ACOS-4 virtual machine architecture
%J Proceedings of the Twelfth Annual International Symposium on Computer Architecture
%C Boston, Massachusetts
%D June 1985
%O published as SIGARCH Computer Architecture News 13:3
%K isca isca12
%P 171-178

%A T.P. Dobry
%A A.M. Despain
%A Y.N. Patt
%T Performance studies of a Prolog machine architecture
%J Proceedings of the Twelfth Annual International Symposium on Computer Architecture
%C Boston, Massachusetts
%D June 1985
%O published as SIGARCH Computer Architecture News 13:3
%K isca isca12
%P 180-190

%A R. Nakazaki
%A A. Konagaya
%A S.-i. Habata
%A H. Shimazu
%A M. Umemura
%A M. Yamamoto
%A M. Yokota
%A T. Chikayama
%T Design of a high-speed Prolog machine (HPM)
%J Proceedings of the Twelfth Annual International Symposium on Computer Architecture
%C Boston, Massachusetts
%D June 1985
%O published as SIGARCH Computer Architecture News 13:3
%K isca isca12
%P 191-197

%A N.S. Woo
%T A hardware unification unit: design and analysis
%J Proceedings of the Twelfth Annual International Symposium on Computer Architecture
%C Boston, Massachusetts
%D June 1985
%O published as SIGARCH Computer Architecture News 13:3
%K isca isca12
%P 198-205

%A N. Matelan
%T The FLEX/32 multicomputer
%J Proceedings of the Twelfth Annual International Symposium on Computer Architecture
%C Boston, Massachusetts
%D June 1985
%O published as SIGARCH Computer Architecture News 13:3
%K isca isca12
%P 209-213

%A D. Naedel
%T Closely coupled asynchronous hierarchical and parallel processing
%J Proceedings of the Twelfth Annual International Symposium on Computer Architecture
%C Boston, Massachusetts
%D June 1985
%O published as SIGARCH Computer Architecture News 13:3
%K isca isca12
%P 215-220

%A J. Savage
%T Parallel processing as a language design problem
%J Proceedings of the Twelfth Annual International Symposium on Computer Architecture
%C Boston, Massachusetts
%D June 1985
%O published as SIGARCH Computer Architecture News 13:3
%K isca isca12
%P 221-224

%A D. Rodgers
%T Improvements in multiprocessor system design
%J Proceedings of the Twelfth Annual International Symposium on Computer Architecture
%C Boston, Massachusetts
%D June 1985
%O published as SIGARCH Computer Architecture News 13:3
%K isca isca12
%P 225-231

%A P.B. Mark
%T The Sequoia computer:
a fault-tolerant tightly-coupled multiprocessor architecture
%J Proceedings of the Twelfth Annual International Symposium on Computer Architecture
%C Boston, Massachusetts
%D June 1985
%O published as SIGARCH Computer Architecture News 13:3
%K isca isca12
%P 232
%O abstract only

%A E. Nestle
%A A. Inselberg
%T The Synapse N+1 system: architectural characteristics and
performance data of a tightly-coupled multiprocessor system
%J Proceedings of the Twelfth Annual International Symposium on Computer Architecture
%C Boston, Massachusetts
%D June 1985
%O published as SIGARCH Computer Architecture News 13:3
%K isca isca12
%P 233-239

%A R.W. Horst
%A T.C.K. Chou
%T An architecture for high volume transaction processing
%J Proceedings of the Twelfth Annual International Symposium on Computer Architecture
%C Boston, Massachusetts
%D June 1985
%O published as SIGARCH Computer Architecture News 13:3
%K isca isca12
%P 240-245

%A S. Kamiya
%A K. Iwata
%A H. Sakai
%A S. Matsuda
%A S. Shibayama
%A K. Murakami
%T Hardware pipeline algorithm for relational database operation
and its implementation using dedicated hardware
%J Proceedings of the Twelfth Annual International Symposium on Computer Architecture
%C Boston, Massachusetts
%D June 1985
%O published as SIGARCH Computer Architecture News 13:3
%K isca isca12
%P 250-257

%A D.L. Lee
%T A distributed multiple-response resolver for value-ordered retrieval
%J Proceedings of the Twelfth Annual International Symposium on Computer Architecture
%C Boston, Massachusetts
%D June 1985
%O published as SIGARCH Computer Architecture News 13:3
%K isca isca12
%P 258-265

%A J. Feo
%A R. Jenevein
%A J.C. Browne
%T Dynamic, distributed resource configuration on SW-Banyans
%J Proceedings of the Twelfth Annual International Symposium on Computer Architecture
%C Boston, Massachusetts
%D June 1985
%O published as SIGARCH Computer Architecture News 13:3
%K isca isca12
%P 268-275

%A R.H. Katz
%A S.J. Eggers
%A D.A. Wood
%A C.L. Perkins
%A R.G. Sheldon
%T Implementing a cache consistency protocol
%J Proceedings of the Twelfth Annual International Symposium on Computer Architecture
%C Boston, Massachusetts
%D June 1985
%O published as SIGARCH Computer Architecture News 13:3
%K isca isca12
%P 276-283

%A Z. Li
%A W. Abu-Sufah
%T A technique for reducing synchronization overhead
in large-scale multiprocessors
%J Proceedings of the Twelfth Annual International Symposium on Computer Architecture
%C Boston, Massachusetts
%D June 1985
%O published as SIGARCH Computer Architecture News 13:3
%K isca isca12
%P 284-291

%A C. Whitby-Stevens
%T The transputer
%J Proceedings of the Twelfth Annual International Symposium on Computer Architecture
%C Boston, Massachusetts
%D June 1985
%O published as SIGARCH Computer Architecture News 13:3
%K isca isca12
%P 292-300

%A A.R. Hurson
%A B. Shirazi
%T A systolic multiplier unit and its VLSI design
%J Proceedings of the Twelfth Annual International Symposium on Computer Architecture
%C Boston, Massachusetts
%D June 1985
%O published as SIGARCH Computer Architecture News 13:3
%K isca isca12
%P 302-309

%A R. Melhem
%T A language for the simulation of systolic architectures
%J Proceedings of the Twelfth Annual International Symposium on Computer Architecture
%C Boston, Massachusetts
%D June 1985
%O published as SIGARCH Computer Architecture News 13:3
%K isca isca12
%P 310-314

%A H.Y.H. Chuang
%A G. He
%T A versatile systolic array for matrix computations
%J Proceedings of the Twelfth Annual International Symposium on Computer Architecture
%C Boston, Massachusetts
%D June 1985
%O published as SIGARCH Computer Architecture News 13:3
%K isca isca12
%P 315-322

%A R. Vedder
%A D. Finn
%T The Hughes data flow processor:
architecture for efficient signal and data processing
%J Proceedings of the Twelfth Annual International Symposium on Computer Architecture
%C Boston, Massachusetts
%D June 1985
%O published as SIGARCH Computer Architecture News 13:3
%K isca isca12
%P 324-332

%A K.R. Traub
%T An abstract parallel graph reduction machine
%J Proceedings of the Twelfth Annual International Symposium on Computer Architecture
%C Boston, Massachusetts
%D June 1985
%O published as SIGARCH Computer Architecture News 13:3
%K isca isca12
%P 333-341

%A B.R. Preiss
%A V.C. Hamacher
%T Data flow on a queue machine
%J Proceedings of the Twelfth Annual International Symposium on Computer Architecture
%C Boston, Massachusetts
%D June 1985
%O published as SIGARCH Computer Architecture News 13:3
%K isca isca12
%P 342-351

%A J.L. Gaudiot
%T Methods for handling structures in data-flow systems
%J Proceedings of the Twelfth Annual International Symposium on Computer Architecture
%C Boston, Massachusetts
%D June 1985
%O published as SIGARCH Computer Architecture News 13:3
%K isca isca12
%P 352-358

%A M.R. Samatham
%A D.K. Pradhan
%T The De Bruijn multiprocessor network: a versatile sorting network
%J Proceedings of the Twelfth Annual International Symposium on Computer Architecture
%C Boston, Massachusetts
%D June 1985
%O published as SIGARCH Computer Architecture News 13:3
%K isca isca12
%P 360-367

%A N.-F. Tzeng
%A P.-C. Yew
%A C.-Q. Zhu
%T A fault-tolerant scheme for multistage interconnection networks
%J Proceedings of the Twelfth Annual International Symposium on Computer Architecture
%C Boston, Massachusetts
%D June 1985
%O published as SIGARCH Computer Architecture News 13:3
%K isca isca12
%P 368-375

%A V.P. Kumar
%A S.M. Reddy
%T Design and analysis of fault-tolerant multistage
interconnection networks with low link complexity
%J Proceedings of the Twelfth Annual International Symposium on Computer Architecture
%C Boston, Massachusetts
%D June 1985
%O published as SIGARCH Computer Architecture News 13:3
%K isca isca12
%P 376-386

%A N.J. Davis, IV
%A H.J. Siegel
%T The performance analysis of partitioned circuit switched
multistage interconnection networks
%J Proceedings of the Twelfth Annual International Symposium on Computer Architecture
%C Boston, Massachusetts
%D June 1985
%O published as SIGARCH Computer Architecture News 13:3
%K isca isca12
%P 387-394

%A D. Vrsalovic
%A E.F. Gehringer
%A Z.Z. Segall
%A D.P. Siewiorek
%T The influence of parallel decomposition strategies
on the performance of multiprocessor systems
%J Proceedings of the Twelfth Annual International Symposium on Computer Architecture
%C Boston, Massachusetts
%D June 1985
%O published as SIGARCH Computer Architecture News 13:3
%K isca isca12
%P 396-405

%A W. Abu-Sufah
%A A.Y. Kwok
%T Performance prediction tools for Cedar:
a multiprocessor supercomputer
%J Proceedings of the Twelfth Annual International Symposium on Computer Architecture
%C Boston, Massachusetts
%D June 1985
%O published as SIGARCH Computer Architecture News 13:3
%K isca isca12
%P 406-413

%A J.M. Llaberia Grino
%A M.V. Cortes
%A E.H. Lillo
%A J.L. Mancho
%T Analysis and simulation of multiplexed single-bus networks
with and without buffering
%J Proceedings of the Twelfth Annual International Symposium on Computer Architecture
%C Boston, Massachusetts
%D June 1985
%O published as SIGARCH Computer Architecture News 13:3
%K isca isca12
%P 414-421

%A J. Sanguinetti
%A B. Kumar
%T Performance of a message-based multiprocessor
%J Proceedings of the Twelfth Annual International Symposium on Computer Architecture
%C Boston, Massachusetts
%D June 1985
%O published as SIGARCH Computer Architecture News 13:3
%K isca isca12
%P 424-425

%A Haruo Yokota
%A Hidenori Itoh
%T A model and an architecture for a relational knowledge base
%J Proceedings of the Thirteenth Annual International Symposium on Computer Architecture
%C Tokyo, Japan
%D June 1986
%O published as SIGARCH Computer Architecture News 14:2
%K isca isca13
%P 2-9

%A Makoto Amamiya
%A Masaru Takesue
%A Ryuzo Hasegawa
%A Hirohide Mikami
%T Implementation and evaluation
of a list-processing-oriented data flow machine
%J Proceedings of the Thirteenth Annual International Symposium on Computer Architecture
%C Tokyo, Japan
%D June 1986
%O published as SIGARCH Computer Architecture News 14:2
%K isca isca13
%P 10-19

%A K. Takahashi
%A H. Yamada
%A H. Nagai
%A K. Matsumi
%T A new string search hardware architecture for VLSI
%J Proceedings of the Thirteenth Annual International Symposium on Computer Architecture
%C Tokyo, Japan
%D June 1986
%O published as SIGARCH Computer Architecture News 14:2
%K isca isca13
%P 20-27

%A Anoop Gupta
%A Charles Forgy
%A Allen Newell
%A Robert Wedig
%T Parallel algorithms and architectures for rule-based systems
%J Proceedings of the Thirteenth Annual International Symposium on Computer Architecture
%C Tokyo, Japan
%D June 1986
%O published as SIGARCH Computer Architecture News 14:2
%K isca isca13
%P 28-37

%A Robert H. Halstead,\ Jr.
%A Thomas I. Anderson
%A Randy B. Osborne
%A Thomas L. Sterling
%T Concert: design of a multiprocessor development system
%J Proceedings of the Thirteenth Annual International Symposium on Computer Architecture
%C Tokyo, Japan
%D June 1986
%O published as SIGARCH Computer Architecture News 14:2
%K isca isca13
%P 40-48

%A H.T. Kung
%T Memory requirements for balanced computer architectures
%J Proceedings of the Thirteenth Annual International Symposium on Computer Architecture
%C Tokyo, Japan
%D June 1986
%O published as SIGARCH Computer Architecture News 14:2
%K isca isca13
%P 49-54

%A Yang-Chang Hong
%A Thomas H. Payne
%A Le Baron O. Ferguson
%T Graph allocation in static dataflow systems
%J Proceedings of the Thirteenth Annual International Symposium on Computer Architecture
%C Tokyo, Japan
%D June 1986
%O published as SIGARCH Computer Architecture News 14:2
%K isca isca13
%P 55-64

%A Prathima Agrawal
%A Rakesh Agrawal
%T Software implementation of a recursive fault tolerance algorithm
on a network of computers
%J Proceedings of the Thirteenth Annual International Symposium on Computer Architecture
%C Tokyo, Japan
%D June 1986
%O published as SIGARCH Computer Architecture News 14:2
%K isca isca13
%P 65-72

%A Tohru Nojiri
%A Shumpei Kawasaki
%A Kousuke Sakoda
%T Microprogrammable processor for object-oriented architecture
%J Proceedings of the Thirteenth Annual International Symposium on Computer Architecture
%C Tokyo, Japan
%D June 1986
%O published as SIGARCH Computer Architecture News 14:2
%K isca isca13
%P 73-81

%A Shreekant S. Thakkar
%A William E. Hostmann
%T An instruction fetch unit for a graph reduction machine
%J Proceedings of the Thirteenth Annual International Symposium on Computer Architecture
%C Tokyo, Japan
%D June 1986
%O published as SIGARCH Computer Architecture News 14:2
%K isca isca13
%P 82-91

%A Edward F. Gehringer
%A Robert P. Colwell
%T Fast object-oriented procedure calls: lessons from the Intel 432
%J Proceedings of the Thirteenth Annual International Symposium on Computer Architecture
%C Tokyo, Japan
%D June 1986
%O published as SIGARCH Computer Architecture News 14:2
%K isca isca13
%P 92-101

%A Daniel M. Dias
%A Balakrishna R. Iyer
%A Philip S. Yu
%T On coupling many small systems for transaction processing
%J Proceedings of the Thirteenth Annual International Symposium on Computer Architecture
%C Tokyo, Japan
%D June 1986
%O published as SIGARCH Computer Architecture News 14:2
%K isca isca13
%P 104-110

%A Mohammad L. Malkawi
%A Janak H. Patel
%T Performance measurement of paging behavior in multiprogramming systems
%J Proceedings of the Thirteenth Annual International Symposium on Computer Architecture
%C Tokyo, Japan
%D June 1986
%O published as SIGARCH Computer Architecture News 14:2
%K isca isca13
%P 111-118

%A Anant Agrawal
%A Richard L. Sites
%A Mark Horowitz
%T ATUM: a new technique for capturing address traces using microcode
%J Proceedings of the Thirteenth Annual International Symposium on Computer Architecture
%C Tokyo, Japan
%D June 1986
%O published as SIGARCH Computer Architecture News 14:2
%K isca isca13
%P 119-127

%A Michael J. Wise
%T Experimenting with EPILOG: some results and preliminary conclusions
%J Proceedings of the Thirteenth Annual International Symposium on Computer Architecture
%C Tokyo, Japan
%D June 1986
%O published as SIGARCH Computer Architecture News 14:2
%K isca isca13
%P 130-139

%A Yasuro Shobatake
%A Hideo Aiso
%T A unification processor based on a uniformly structured cellular hardware
%J Proceedings of the Thirteenth Annual International Symposium on Computer Architecture
%C Tokyo, Japan
%D June 1986
%O published as SIGARCH Computer Architecture News 14:2
%K isca isca13
%P 140-148

%A Noriyoshi Ito
%A Masatoshi Sato
%A Eiji Kuno
%A Kazuaki Rokusawa
%T The architecture and preliminary evaluation results
of the experimental parallel inference machine PIM-D
%J Proceedings of the Thirteenth Annual International Symposium on Computer Architecture
%C Tokyo, Japan
%D June 1986
%O published as SIGARCH Computer Architecture News 14:2
%K isca isca13
%P 149-156

%A Andre Seznec
%T An efficient routing control unit for the Sigma network SIGMA^(4)
%J Proceedings of the Thirteenth Annual International Symposium on Computer Architecture
%C Tokyo, Japan
%D June 1986
%O published as SIGARCH Computer Architecture News 14:2
%K isca isca13
%P 158-168

%A J.D. Nicoud
%A K. Skala
%T RESYM, a high performance, low power multi-microprocessor bus
%J Proceedings of the Thirteenth Annual International Symposium on Computer Architecture
%C Tokyo, Japan
%D June 1986
%O published as SIGARCH Computer Architecture News 14:2
%K isca isca13
%P 169-174

%A Kyungsook Yoon Lee
%A Wael Hegazy
%T The extra stage Gamma network
%J Proceedings of the Thirteenth Annual International Symposium on Computer Architecture
%C Tokyo, Japan
%D June 1986
%O published as SIGARCH Computer Architecture News 14:2
%K isca isca13
%P 175-182

%A Masanobu Yuhara
%A Aikira Hattori
%A Masashi Niwa
%A Mitsuhiro Kishimoto
%A Hiromu Hayashi
%T Evaluation of the FACOM Alpha Lisp machine
%J Proceedings of the Thirteenth Annual International Symposium on Computer Architecture
%C Tokyo, Japan
%D June 1986
%O published as SIGARCH Computer Architecture News 14:2
%K isca isca13
%P 183-190

%A A.R. Pleszkun
%A M.J. Thazhuthaveetil
%T An architecture for efficient Lisp list access
%J Proceedings of the Thirteenth Annual International Symposium on Computer Architecture
%C Tokyo, Japan
%D June 1986
%O published as SIGARCH Computer Architecture News 14:2
%K isca isca13
%P 191-198

%A Toshiyuki Nakata
%A NobuhikoKoike
%T A functional level simulation engine of MAN-YO
- a special purpose parallel machine for logic design automation
%J Proceedings of the Thirteenth Annual International Symposium on Computer Architecture
%C Tokyo, Japan
%D June 1986
%O published as SIGARCH Computer Architecture News 14:2
%K isca isca13
%P 202-208

%A Edward H. Frank
%T Exploiting parallelism in a switch-level simulation machine
%J Proceedings of the Thirteenth Annual International Symposium on Computer Architecture
%C Tokyo, Japan
%D June 1986
%O published as SIGARCH Computer Architecture News 14:2
%K isca isca13
%P 209-215

%A T.S. Anantharaman
%A R. Bisiani
%T A hardware accelerator for speech recognition algorithms
%J Proceedings of the Thirteenth Annual International Symposium on Computer Architecture
%C Tokyo, Japan
%D June 1986
%O published as SIGARCH Computer Architecture News 14:2
%K isca isca13
%P 216-223

%A Toshio Shimada
%A Kei Hiraki
%A Kenji Nishida
%A Satoshi Sekiguchi
%T Evaluation of a prototype data flow processor of the SIGMA-1
for scientific computations
%J Proceedings of the Thirteenth Annual International Symposium on Computer Architecture
%C Tokyo, Japan
%D June 1986
%O published as SIGARCH Computer Architecture News 14:2
%K isca isca13
%P 224-234

%A J. Sargeant
%A C.C. Kirkham
%T Stored data structures on the Manchester dataflow machine
%J Proceedings of the Thirteenth Annual International Symposium on Computer Architecture
%C Tokyo, Japan
%D June 1986
%O published as SIGARCH Computer Architecture News 14:2
%K isca isca13
%P 235-242

%A K. Kawakami
%A J.R. Gurd
%T A scalable dataflow structure store
%J Proceedings of the Thirteenth Annual International Symposium on Computer Architecture
%C Tokyo, Japan
%D June 1986
%O published as SIGARCH Computer Architecture News 14:2
%K isca isca13
%P 243-250

%A Makoto Hasegawa
%A Yoshiharu Shigei
%T AT^2 = O(N log^4 N), T = O(log N) fast Fourier transform
in a light connected 3-dimensional VLSI
%J Proceedings of the Thirteenth Annual International Symposium on Computer Architecture
%C Tokyo, Japan
%D June 1986
%O published as SIGARCH Computer Architecture News 14:2
%K isca isca13
%P 252-260

%A K. Sapiecha
%A R. Jarocki
%T Modular architecture for high performance implementation of FFT algorithm
%J Proceedings of the Thirteenth Annual International Symposium on Computer Architecture
%C Tokyo, Japan
%D June 1986
%O published as SIGARCH Computer Architecture News 14:2
%K isca isca13
%P 261-270

%A Juan J. Navarro
%A Jose M. Llaberia
%A Mateo Valero
%T Computing size-independent matrix problems on systolic array processors
%J Proceedings of the Thirteenth Annual International Symposium on Computer Architecture
%C Tokyo, Japan
%D June 1986
%O published as SIGARCH Computer Architecture News 14:2
%K isca isca13
%P 271-278

%A Shinji Tomita
%A Kiyoshi Shibayama
%A Toshiyuki Nakata
%A Shinji Yuasa
%A Hiroshi Hagiwara
%T A computer with low-level parallelism QA-2
- its applications to 3-D graphics and Prolog/Lisp machines
%J Proceedings of the Thirteenth Annual International Symposium on Computer Architecture
%C Tokyo, Japan
%D June 1986
%O published as SIGARCH Computer Architecture News 14:2
%K isca isca13
%P 280-289

%A Masaharu Hirayama
%T VLSI oriented asynchronous architecture
%J Proceedings of the Thirteenth Annual International Symposium on Computer Architecture
%C Tokyo, Japan
%D June 1986
%O published as SIGARCH Computer Architecture News 14:2
%K isca isca13
%P 290-296

%A Wen-mei Hwu
%A Yale N. Patt
%T HPSm, a high performance restricted data flow architecture
having minimal functionality
%J Proceedings of the Thirteenth Annual International Symposium on Computer Architecture
%C Tokyo, Japan
%D June 1986
%O published as SIGARCH Computer Architecture News 14:2
%K isca isca13
%P 297-306

%A Kenji Onaga
%A Takahiro Takechi
%T On design of rotary array communication and wavefront-driven algorithms
for solving large-scale band-limited matrix equations
%J Proceedings of the Thirteenth Annual International Symposium on Computer Architecture
%C Tokyo, Japan
%D June 1986
%O published as SIGARCH Computer Architecture News 14:2
%K isca isca13
%P 308-315

%A Leonard M. Napolitano,\ Jr.
%T A computer architecture for dynamic finite element analysis
%J Proceedings of the Thirteenth Annual International Symposium on Computer Architecture
%C Tokyo, Japan
%D June 1986
%O published as SIGARCH Computer Architecture News 14:2
%K isca isca13
%P 316-323

%A D.T. Harper,\ III
%A J.R. Jump
%T Performance evaluation of vector accesses
in parallel memories using a skewed storage scheme
%J Proceedings of the Thirteenth Annual International Symposium on Computer Architecture
%C Tokyo, Japan
%D June 1986
%O published as SIGARCH Computer Architecture News 14:2
%K isca isca13
%P 324-328

%A Toshio Kondo
%A Toshio Tsuchiya
%A Yoshihiro Kitamura
%A Yoshi Sugiyama
%A Takashi Kimura
%A Takayoshi Nakashima
%T Pseudo MIMD array processor - AAP2
%J Proceedings of the Thirteenth Annual International Symposium on Computer Architecture
%C Tokyo, Japan
%D June 1986
%O published as SIGARCH Computer Architecture News 14:2
%K isca isca13
%P 330-337

%A Allan L. Fisher
%T Scan line array processors for image computation
%J Proceedings of the Thirteenth Annual International Symposium on Computer Architecture
%C Tokyo, Japan
%D June 1986
%O published as SIGARCH Computer Architecture News 14:2
%K isca isca13
%P 338-345

%A Marco Annaratone
%A Emmenual Arnould
5A Thomas Gross
%A H.T. Kung
%A Monica S. Lam
%A Onat Menzilcioglu
%A Ken Sarocky
%A Jon A. Webb
%T Warp architecture and implementation
%J Proceedings of the Thirteenth Annual International Symposium on Computer Architecture
%C Tokyo, Japan
%D June 1986
%O published as SIGARCH Computer Architecture News 14:2
%K isca isca13
%P 346-356

%A David A. Wood
%A Susan J. Eggers
%A Garth Gibson
%A Mark D. Hill
%A Joan M. Pendleton
%A Scott A. Ritchie
%A George S. Taylor
%A Randy H. Katz
%A David A. Patterson
%T An in-cache address translation mechanism
%J Proceedings of the Thirteenth Annual International Symposium on Computer Architecture
%C Tokyo, Japan
%D June 1986
%O published as SIGARCH Computer Architecture News 14:2
%K isca isca13
%P 358-365

%A David R. Cheriton
%A Gert A. Slavenburg
%A Patrick D. Boyle
%T Software-controlled caches in the VMP microprocessor
%J Proceedings of the Thirteenth Annual International Symposium on Computer Architecture
%C Tokyo, Japan
%D June 1986
%O published as SIGARCH Computer Architecture News 14:2
%K isca isca13
%P 366-374

%A James R. Goodman
%A Wei-Chung Hsu
%T On the use of registers vs. cache to minimize memory traffic
%J Proceedings of the Thirteenth Annual International Symposium on Computer Architecture
%C Tokyo, Japan
%D June 1986
%O published as SIGARCH Computer Architecture News 14:2
%K isca isca13
%P 375-383

%A Peter Y.T. Hsu
%A Edward S. Davidson
%T Highly concurrent scalar processing
%J Proceedings of the Thirteenth Annual International Symposium on Computer Architecture
%C Tokyo, Japan
%D June 1986
%O published as SIGARCH Computer Architecture News 14:2
%K isca isca13
%P 386-395

%A Scott McFarling
%A John Hennessy
%T Reducing the cost of branches
%J Proceedings of the Thirteenth Annual International Symposium on Computer Architecture
%C Tokyo, Japan
%D June 1986
%O published as SIGARCH Computer Architecture News 14:2
%K isca isca13
%P 396-403

%A Steven R. Kunkel
%A James E. Smith
%T Optimal pipelining in supercomputers
%J Proceedings of the Thirteenth Annual International Symposium on Computer Architecture
%C Tokyo, Japan
%D June 1986
%O published as SIGARCH Computer Architecture News 14:2
%K isca isca13
%P 404-411

%A Paul Sweazey
%A Alan Jay Smith
%T A class of compatible cache consistency protocols
and their support by the IEEE Futurebus
%J Proceedings of the Thirteenth Annual International Symposium on Computer Architecture
%C Tokyo, Japan
%D June 1986
%O published as SIGARCH Computer Architecture News 14:2
%K isca isca13
%P 414-423

%A Philip Bitar
%A Alvin M. Despain
%T Multiprocessor cache synchronization - issues, innovations, evolution
%J Proceedings of the Thirteenth Annual International Symposium on Computer Architecture
%C Tokyo, Japan
%D June 1986
%O published as SIGARCH Computer Architecture News 14:2
%K isca isca13
%P 424-433

%A Michel Dubois
%A Christoph Scheurich
%A Faye Briggs
%T Memory access buffering in multiprocessors
%J Proceedings of the Thirteenth Annual International Symposium on Computer Architecture
%C Tokyo, Japan
%D June 1986
%O published as SIGARCH Computer Architecture News 14:2
%K isca isca13
%P 434-442

%A George S. Taylor
%A Paul N. Hilfinger
%A James R. Larus
%A David A. Patterson
%A Benjamin G. Zorn
%T Evaluation of the SPUR Lisp architecture
%J Proceedings of the Thirteenth Annual International Symposium on Computer Architecture
%C Tokyo, Japan
%D June 1986
%O published as SIGARCH Computer Architecture News 14:2
%K isca isca13
%P 444-452

%A David R. Ditzel
%A Hubert R. McLellan
%T Branch folding in the CRISP microprocessor: reducing branch delay to zero
%J Proceedings of the Fourteenth Annual International Symposium on Computer Architecture
%C Pittsburgh, Pennsylvania
%D June 1987
%O published as SIGARCH Computer Architecture News 15:2
%K isca isca14
%P 2-9

%A John A. DeRosa
%A Henry M. Levy
%T An evaluation of branch architectures
%J Proceedings of the Fourteenth Annual International Symposium on Computer Architecture
%C Pittsburgh, Pennsylvania
%D June 1987
%O published as SIGARCH Computer Architecture News 15:2
%K isca isca14
%P 10-16

%A Wen-mei W. Hwu
%A Yale N. Patt
%T Checkpoint repair for out-of-order execution machines
%J Proceedings of the Fourteenth Annual International Symposium on Computer Architecture
%C Pittsburgh, Pennsylvania
%D June 1987
%O published as SIGARCH Computer Architecture News 15:2
%K isca isca14
%P 18-26

%A Gurindar S. Sohi
%A Sriram Vajapeyam
%T Instruction issue logic
for high performance, interruptable pipeline processors
%J Proceedings of the Fourteenth Annual International Symposium on Computer Architecture
%C Pittsburgh, Pennsylvania
%D June 1987
%O published as SIGARCH Computer Architecture News 15:2
%K isca isca14
%P 27-34

%A John Swensen
%A Yale Patt
%T Fast temporary storage for serial and parallel execution
%J Proceedings of the Fourteenth Annual International Symposium on Computer Architecture
%C Pittsburgh, Pennsylvania
%D June 1987
%O published as SIGARCH Computer Architecture News 15:2
%K isca isca14
%P 35-43

%A Ken Wong
%A Mark A. Franklin
%T Performance analysis and design of a logic simulation machine
%J Proceedings of the Fourteenth Annual International Symposium on Computer Architecture
%C Pittsburgh, Pennsylvania
%D June 1987
%O published as SIGARCH Computer Architecture News 15:2
%K isca isca14
%P 46-55

%A Kshitij Doshi
%A Peter Varman
%T A modular systolic architecture for image convolutions
%J Proceedings of the Fourteenth Annual International Symposium on Computer Architecture
%C Pittsburgh, Pennsylvania
%D June 1987
%O published as SIGARCH Computer Architecture News 15:2
%K isca isca14
%P 56-63

%A Satoshi Fujita
%A Reiji Aibara
%A Masafuni Yamashita
%A Tadashi Ae
%T A template matching algorithm using optically-connected 3-D VLSI architecture
%J Proceedings of the Fourteenth Annual International Symposium on Computer Architecture
%C Pittsburgh, Pennsylvania
%D June 1987
%O published as SIGARCH Computer Architecture News 15:2
%K isca isca14
%P 64-70

%A Bilha Mendelson
%A Gabriel M. Silberman
%T Mapping data flow programs on a VLSI array of processors
%J Proceedings of the Fourteenth Annual International Symposium on Computer Architecture
%C Pittsburgh, Pennsylvania
%D June 1987
%O published as SIGARCH Computer Architecture News 15:2
%K isca isca14
%P 72-80

%A Dipak Ghosal
%A L.xmi N. Bhuayn
%T Analytical modeling and architectural modications of a dataflow computer
%J Proceedings of the Fourteenth Annual International Symposium on Computer Architecture
%C Pittsburgh, Pennsylvania
%D June 1987
%O published as SIGARCH Computer Architecture News 15:2
%K isca isca14
%P 81-89

%A Masaru Takesue
%T A unified resource management and execution control mechanism
for data flow machines
%J Proceedings of the Fourteenth Annual International Symposium on Computer Architecture
%C Pittsburgh, Pennsylvania
%D June 1987
%O published as SIGARCH Computer Architecture News 15:2
%K isca isca14
%P 90-97
%K DFM-II

%A S. Abe
%A T. Bandoh
%A S. Yamaguchi
%A K. Kurosawa
%A K. Kiriyama
%T High performance integrated Prolog processor IPP
%J Proceedings of the Fourteenth Annual International Symposium on Computer Architecture
%C Pittsburgh, Pennsylvania
%D June 1987
%O published as SIGARCH Computer Architecture News 15:2
%K isca isca14
%P 100-107

%A Barry S. Fagin
%A Alvin M. Despain
%T Performance studies of a parallel Prolog architecture
%J Proceedings of the Fourteenth Annual International Symposium on Computer Architecture
%C Pittsburgh, Pennsylvania
%D June 1987
%O published as SIGARCH Computer Architecture News 15:2
%K isca isca14
%P 108-116
%K Aquarius, PPP

%A P.L. Civera
%A F. Maddaleno
%A G.L. Piccinini
%A M. Zamboni
%T An experimental VLSI Prolog interpreter: preliminary measurements and results
%J Proceedings of the Fourteenth Annual International Symposium on Computer Architecture
%C Pittsburgh, Pennsylvania
%D June 1987
%O published as SIGARCH Computer Architecture News 15:2
%K isca isca14
%P 117-126

%A Oliver Ridoux
%T Deterministic and stochastic modeling of parallel garbage collection
- towards real-time criteria
%J Proceedings of the Fourteenth Annual International Symposium on Computer Architecture
%C Pittsburgh, Pennsylvania
%D June 1987
%O published as SIGARCH Computer Architecture News 15:2
%K isca isca14
%P 128-136

%A Sun Chengzheng
%A Tzu Yungui
%T The sharing of environment in AND-OR-parallel execution of logic programs
%J Proceedings of the Fourteenth Annual International Symposium on Computer Architecture
%C Pittsburgh, Pennsylvania
%D June 1987
%O published as SIGARCH Computer Architecture News 15:2
%K isca isca14
%P 137-144

%A Aloke Guha
%A Raja Ramnarayan
%A Matthew Derstine
%T Architectural issues in designing symbolic processors in optics
%J Proceedings of the Fourteenth Annual International Symposium on Computer Architecture
%C Pittsburgh, Pennsylvania
%D June 1987
%O published as SIGARCH Computer Architecture News 15:2
%K isca isca14
%P 145-151

%A Anujan Varma
%A C.S. Raghavendra
%T Rearrangeability of multistage shuffle/exchange networks
%J Proceedings of the Fourteenth Annual International Symposium on Computer Architecture
%C Pittsburgh, Pennsylvania
%D June 1987
%O published as SIGARCH Computer Architecture News 15:2
%K isca isca14
%P 154-162

%A Ramon Beivide
%A Enrique Herrada
%A Jose L. Balcazar
%A Jesus Labarta
%T Optimized mesh-connected networks for SIMD and MIMD architectures
%J Proceedings of the Fourteenth Annual International Symposium on Computer Architecture
%C Pittsburgh, Pennsylvania
%D June 1987
%O published as SIGARCH Computer Architecture News 15:2
%K isca isca14
%P 163-170

%A D.T. Harper, III
%A J.R. Jump
%T Performance evaluation
of reduced bandwidth multistage interconnection networks
%J Proceedings of the Fourteenth Annual International Symposium on Computer Architecture
%C Pittsburgh, Pennsylvania
%D June 1987
%O published as SIGARCH Computer Architecture News 15:2
%K isca isca14
%P 171-175

%A Umakishore Ramachandran
%A Marvin Solomon
%A Mary Vernon
%T Hardware support for interprocess communication
%J Proceedings of the Fourteenth Annual International Symposium on Computer Architecture
%C Pittsburgh, Pennsylvania
%D June 1987
%O published as SIGARCH Computer Architecture News 15:2
%K isca isca14
%P 178-188

%A William J. Dally
%A Linda Chao
%A Andrew Chien
%A Soha Hassoun
%A Waldemar Horwat
%A Jon Kaplan
%A Paul Song
%A Brian Totty
%A Scott Wills
%T Architecture of a message-driven processor
%J Proceedings of the Fourteenth Annual International Symposium on Computer Architecture
%C Pittsburgh, Pennsylvania
%D June 1987
%O published as SIGARCH Computer Architecture News 15:2
%K isca isca14
%P 189-196
%K MDP

%A Manoj Kumar
%T Effect of storage allocation/reclamation methods
on parallelism and storage requirements
%J Proceedings of the Fourteenth Annual International Symposium on Computer Architecture
%C Pittsburgh, Pennsylvania
%D June 1987
%O published as SIGARCH Computer Architecture News 15:2
%K isca isca14
%P 197-205

%A J.H. Chang
%A H. Chao
%A K. So
%T Cache design of a sub-micron CMOS System/370
%J Proceedings of the Fourteenth Annual International Symposium on Computer Architecture
%C Pittsburgh, Pennsylvania
%D June 1987
%O published as SIGARCH Computer Architecture News 15:2
%K isca isca14
%P 208-213

%A Martin Freeman
%T An architectural perspective on a memory access controller
%J Proceedings of the Fourteenth Annual International Symposium on Computer Architecture
%C Pittsburgh, Pennsylvania
%D June 1987
%O published as SIGARCH Computer Architecture News 15:2
%K isca isca14
%P 214-223

%A Kifung Cheung
%A Gurindar Sohi
%A Kewal Saluja
%A Dhiraj Pradhan
%T Organization and analysis of a gracefully-degrading interleaved memory system
%J Proceedings of the Fourteenth Annual International Symposium on Computer Architecture
%C Pittsburgh, Pennsylvania
%D June 1987
%O published as SIGARCH Computer Architecture News 15:2
%K isca isca14
%P 224-231

%A Christoph Scheurich
%A Michel Dubois
%T Correct memory operation of cache-based multiprocessors
%J Proceedings of the Fourteenth Annual International Symposium on Computer Architecture
%C Pittsburgh, Pennsylvania
%D June 1987
%O published as SIGARCH Computer Architecture News 15:2
%K isca isca14
%P 234-243

%A Andrew W. Wilson,\ Jr.
%T Hierarchical cache/bus architecture for shared memory multiprocessors
%J Proceedings of the Fourteenth Annual International Symposium on Computer Architecture
%C Pittsburgh, Pennsylvania
%D June 1987
%O published as SIGARCH Computer Architecture News 15:2
%K isca isca14
%P 244-252
%K Encore

%A Roland L. Lee
%A Pen-Chung Yew
%A Duncan H. Lawrie
%T Multiprocessor cache design considerations
%J Proceedings of the Fourteenth Annual International Symposium on Computer Architecture
%C Pittsburgh, Pennsylvania
%D June 1987
%O published as SIGARCH Computer Architecture News 15:2
%K isca isca14
%P 253-262

%A Richard J. Eickemeyer
%A Janak H. Patel
%T Performance evaluation of multiple register sets
%J Proceedings of the Fourteenth Annual International Symposium on Computer Architecture
%C Pittsburgh, Pennsylvania
%D June 1987
%O published as SIGARCH Computer Architecture News 15:2
%K isca isca14
%P 264-271

%A Timothy J. Stanley
%A Robert G. Wedig
%T A performance analysis of automatically managed top of stack buffers
%J Proceedings of the Fourteenth Annual International Symposium on Computer Architecture
%C Pittsburgh, Pennsylvania
%D June 1987
%O published as SIGARCH Computer Architecture News 15:2
%K isca isca14
%P 272-281

%A Brian Moore
%A Andris Padegs
%A Ron Smith
%A Werner Buchholz
%T Concepts of the System/370 vector architecture
%J Proceedings of the Fourteenth Annual International Symposium on Computer Architecture
%C Pittsburgh, Pennsylvania
%D June 1987
%O published as SIGARCH Computer Architecture News 15:2
%K isca isca14
%P 282-288

%A A.R. Pleszkun
%A J.R. Goodman
%A W-C. Hsu
%A R.T. Joersz
%A G. Bier
%A P. Woest
%A P.B. Schechter
%T WISQ: a restartable architecture using queues
%J Proceedings of the Fourteenth Annual International Symposium on Computer Architecture
%C Pittsburgh, Pennsylvania
%D June 1987
%O published as SIGARCH Computer Architecture News 15:2
%K isca isca14
%P 290-299

%A Paul Chow
%A Mark Horowitz
%T Architectural tradeoffs in the design of MIPS-X
%J Proceedings of the Fourteenth Annual International Symposium on Computer Architecture
%C Pittsburgh, Pennsylvania
%D June 1987
%O published as SIGARCH Computer Architecture News 15:2
%K isca isca14
%P 300-308

%A David R. Ditzel
%A Hubert R. McLellan
%A Alan D. Berenbaum
%T The hardware architecture of the CRISP microprocessor
%J Proceedings of the Fourteenth Annual International Symposium on Computer Architecture
%C Pittsburgh, Pennsylvania
%D June 1987
%O published as SIGARCH Computer Architecture News 15:2
%K isca isca14
%P 309-319