%A T.S. Anantharaman
%T A delay insensitive regular expression recognizer
%J IEEE VLSI Technical Bulletin
%K vlsi_tb
%V 1
%N 2
%D September 1986
%P 3-15

%A Mark Hofmann
%T A table-driven approach to timing analysis
%J IEEE VLSI Technical Bulletin
%K vlsi_tb
%V 1
%N 2
%D September 1986
%P 16-18

%A M.J. Foster
%T Avoiding latch formation in regular expression analyzers
%J IEEE VLSI Technical Bulletin
%K vlsi_tb
%V 1
%N 2
%D September 1986
%P 19-28

%A S. Rajgopal
%A S. Ghatak
%A J. McNair
%A S. Kumar
%A D. Bouldin
%T A VLSI implementation of the parallel enumeration sort technique
%J IEEE VLSI Technical Bulletin
%K vlsi_tb
%V 1
%N 3
%D December 1986
%P 35-42

%A Y.C. Hsu
%A W.J. Kubitz
%T A procedure for a chip floor plan
%J IEEE VLSI Technical Bulletin
%K vlsi_tb
%V 1
%N 3
%D December 1986
%P 43-59