%A C. Svensson %T VLSI physics %D 1983 %J Integration %K vlsi %V 1 %N 1 %P 3-20 %A M. Burstein %A R. Pelavin %T Hierarchical channel router %D 1983 %J Integration %K vlsi %V 1 %N 1 %P 21-38 %A J. Vuillemin %T A very fast multiplication algorithm for VLSI implementation %D 1983 %J Integration %K vlsi %V 1 %N 1 %P 39-52 %A S. Goto %A T. Matsuda %A K. Takamizawa %A T. Fujita %A H. Mizumura %A H. Nakamura %A F. Kitajima %T LAMBDA, and integrated master-slice LSI CAD system %D 1983 %J Integration %K vlsi %V 1 %N 1 %P 53-70 %A G. Grassl %A H.-J. Pfleiderer %T A function-independent self-test for large programmable logic arrays %D 1983 %J Integration %K vlsi %V 1 %N 1 %P 71-80 %A H.J. Wassink %A L. Spaanenburg %T Logic gate characterization through ringoscillators %D 1983 %J Integration %K vlsi %V 1 %N 1 %P 81-86 %A H.K.E. Liesenberg %A D.J. Kinniment %T An autolayout system for a hierarchical i.c. design environment %D 1983 %J Integration %K vlsi %V 1 %N 2&3 %P 107-120 %A G.J. Milne %T CIRCAL: a calculus for circuit description %D 1983 %J Integration %K vlsi %V 1 %N 2&3 %P 121-160 %A J.A. Bergstra %A J.W. Klop %T A proof rule for restoring logic circuits %D 1983 %J Integration %K vlsi %V 1 %N 2&3 %P 161-178 %A M. Schlag %A Y.-Z. Liao %A C.K. Wong %T An algorithm for optimal two-dimensional compaction of VLSI layouts %D 1983 %J Integration %K vlsi %V 1 %N 2&3 %P 179-210 %A M. Karpovsky %A L. Levitin %T Detection and identification of input/output stuck-at and bridging faults in combinational and sequential VLSI networks by universal tests %D 1983 %J Integration %K vlsi %V 1 %N 2&3 %P 211-232 %A G. Alia %T VLSI systolic arrays for band matrix multiplication %D 1983 %J Integration %K vlsi %V 1 %N 2&3 %P 233-250 %A A. Halaas %T A systolic VLSI matrix for a family of fundamental searching algorithms %D 1983 %J Integration %K vlsi %V 1 %N 4 %P 269-282 %A R.K. Cavin,\ III %A N.R. Strader,\ II %T Microelectronic architectures and devices for signal and symbol processing %D 1983 %J Integration %K vlsi %V 1 %N 4 %P 283-304 %A J. Ja' Ja' %A R.M. Owens %T An architecture for a VLSI FFT processor %D 1983 %J Integration %K vlsi %V 1 %N 4 %P 305-316 %A M.A. Bayoumi %A G.A. Jullien %A W.C. Miller %T An area-time efficient NMOS adder %D 1983 %J Integration %K vlsi %V 1 %N 4 %P 317-334 %A C. Piguet %T Design methodology for full custom CMOS microcomputers %D 1983 %J Integration %K vlsi %V 1 %N 4 %P 335-350 %A O. Olesen %A C.M. Svensson %T NORCHIP, a silicon brokers model %D 1984 %J Integration %K vlsi %V 2 %N 1 %P 3-14 %A A.B. Cremers %A S.-Y. Kung %T On programming VLSI concurrent array processors %D 1984 %J Integration %K vlsi %V 2 %N 1 %P 15-26 %A Qingjian Yu %A O. Wing %T PLMAP - a piecewise linear MOS circuit analysis program %D 1984 %J Integration %K vlsi %V 2 %N 1 %P 27-48 %A D. Svanaes %A E.J. Aas %T Test generation through logic programming %D 1984 %J Integration %K vlsi %V 2 %N 1 %P 49-68 %A N.P. van der Meijs %A J.T. Fokkema %T VLSI circuit reconstruction from mask topology %D 1984 %J Integration %K vlsi %V 2 %N 2 %P 85-120 %A L. Silvestri %A S. Garue %A M. Marchente %T An heuristic SPICE2-based approach for 2D IIL device simulation %D 1984 %J Integration %K vlsi %V 2 %N 2 %P 121-132 %A G. Alia %A F. Barsi %A E. Martinelli %T A fast near optimum VLSI implementation of FFT using residue number systems %D 1984 %J Integration %K vlsi %V 2 %N 2 %P 133-148 %A R.H. Mak %T Optimization of programmable logic arrays %D 1984 %J Integration %K vlsi %V 2 %N 2 %P 149-162 %A K. Melhorn %T AT2-optimal VLSI integer division and integer square rooting %D 1984 %J Integration %K vlsi %V 2 %N 2 %P 163-168 %A M.A. Bayoumi %A G.A. Jullien %A W.C. Miller %T A VLSI model for residue number system architectures %D 1984 %J Integration %K vlsi %V 2 %N 3 %P 191-212 %A H.C. Yung %A C.R. Allen %A H.K.E. Liesenberg %A D.J. Kinniment %T A recursive design methodology for VLSI: theory and example %D 1984 %J Integration %K vlsi %V 2 %N 3 %P 213-226 %A D.P. LaPotin %A S.R. Nassif %A J.V. Rajan %A M.L. Bushnell %A J.A. Nestor %T DIF: a framework for VLSI multi-level representation %D 1984 %J Integration %K vlsi %V 2 %N 3 %P 227-242 %A C. Moraga %T On a case of symbiosis between systolic arrays %D 1984 %J Integration %K vlsi %V 2 %N 3 %P 243-254 %A M.D.F. Schlag %A L.S. Woo %A C.K. Wong %T Maximizing pin alignment by pin permutations %D 1984 %J Integration %K vlsi %V 2 %N 4 %P 279-308 %A K.K. Saluja %A Kim Thang Le %T Testable design of large random access memories %D 1984 %J Integration %K vlsi %V 2 %N 4 %P 309-330 %A K.O. Arisland %A A.C. Aasbo %A A. Nundal %T VLSI parallel shift sort algorithm and design %D 1984 %J Integration %K vlsi %V 2 %N 4 %P 331-348 %A Susumu Nitta %A Masahiko Kawamura %A Kanji Hirabayashi %T Test generation by activation and defect-drive (TEGAD) %D 1985 %J Integration %K vlsi %V 3 %N 1 %P 3-12 %A Sanjay V. Rajopadhye %A P.A. Subrahmanyam %T Formal semantics for a symbolic IC design technique: examples and applications %D 1985 %J Integration %K vlsi %V 3 %N 1 %P 13-32 %A Qingjian Yu %A Omar Wing %T Interval-graph-based PLA folding %D 1985 %J Integration %K vlsi %V 3 %N 1 %P 33-48 %A Marloes L.P. van\ Lierop %T A flexible bottom-up approach for layout generation %D 1985 %J Integration %K vlsi %V 3 %N 1 %P 49-59 %A Matthew Yuschik %A Hideaki Kobayashi %T Top-down design of a VLSI digital filter bank %D 1985 %J Integration %K vlsi %V 3 %N 2 %P 75-91 %A Werner Schiele %T Automatic design rule adaptation of leaf cell layouts %D 1985 %J Integration %K vlsi %V 3 %N 2 %P 93-112 %A Jerome M. Kurtzberg %A Ellen J. Yoffa %T ACE: a congestion estimator for wiring custom chips %D 1985 %J Integration %K vlsi %V 3 %N 2 %P 113-127 %A W.K. Luk %T A greedy switch-box router %D 1985 %J Integration %K vlsi %V 3 %N 2 %P 129-149 %A David Elliot Shaw %A Theodore M. Sabety %T The multiple-processor PPS chip of the NON-VON 3 supercomputer %D 1985 %J Integration %K vlsi %V 3 %N 3 %P 161-174 %A R.A. Evans %A J.D. Morison %T Architectures for language recognition %D 1985 %J Integration %K vlsi %V 3 %N 3 %P 175-187 %A Werner Grass %T Some results on the design of regular structured sequential circuits %D 1985 %J Integration %K vlsi %V 3 %N 3 %P 189-210 %A B. Codenotti %A F. Romani %A G. Lotti %T VLSI implementation of iterative methods for the solution of linear systems %D 1985 %J Integration %K vlsi %V 3 %N 3 %P 211-221 %A Walter Kraft %A Werner Hein %T A router for channels of nonuniform width containing preplaced wiring and obstacles %D 1985 %J Integration %K vlsi %V 3 %N 3 %P 223-244 %A M. Renovelli %A G. Cambon %A D. Auvergne %T FSPICE: a tool for fault modelling in MOS circuits %D 1985 %J Integration %K vlsi %V 3 %N 3 %P 245-255 %A J.G. Gay %A Roy Richter %T Component placement in VLSI circuits using a constant pressure Monte Carlo method %D 1985 %J Integration %K vlsi %V 3 %N 4 %P 271-282 %A Eric Gullichsen %T Heuristic circuit simulation using Prolog %D 1985 %J Integration %K vlsi %V 3 %N 4 %P 283-318 %A N. Kanopoulos %A V. Makios %T A single-chip adaptive delta modulator with optimum performance %D 1985 %J Integration %K vlsi %V 3 %N 4 %P 319-328 %A Marco Annaratone %T SPLASH: a framework for chip design and layout %D 1985 %J Integration %K vlsi %V 3 %N 4 %P 329-345 %A Fabrizio Luccio %T Access to rows and columns of a rectangular array in a concentric-loop bubble memory %D 1985 %J Integration %K vlsi %V 3 %N 4 %P 347-354 %A John C. Peterson %A Kent F. Smith %T MASHER: an automatic VLSI layout system %D 1986 %J Integration %K vlsi %V 4 %N 1 %P 3-33 %A J.S.T. Huang %A J.M. Daughton %T Yield optimization in wafer scale circuits with hierarchical redundancies %D 1986 %J Integration %K vlsi %V 4 %N 1 %P 43-51 %A W.F. Clocksin %A M.E. Leeser %T Automatic determination of signal flow through MOS transistor networks %D 1986 %J Integration %K vlsi %V 4 %N 1 %P 53-63 %A Hans-Werner Lang %T The instruction systolic array - a parallel architecture for VLSI %D 1986 %J Integration %K vlsi %V 4 %N 1 %P 65-74 %A Christer Svensson %T Signal resynchronization in VLSI systems %D 1986 %J Integration %K vlsi %V 4 %N 1 %P 75-80 %A T.-A. Chu %T On the models for designing VLSI asynchronous digital systems %J Integration %K vlsi %V 4 %N 2 %D June 1986 %P 99-114 %A H. Miyashita %A T. Adachi %A K. Ueda %T An automatic cell pattern generation system for CMOS transistor-pair array LSI %J Integration %K vlsi %V 4 %N 2 %D June 1986 %P 115-134 %A C.T. Wang %T VLSI architecture for device simulation %J Integration %K vlsi %V 4 %N 2 %D June 1986 %P 135-154 %A E. Dijkstra %A C. Piguet %T On minimizing memory in systolic arrays for the dynamic time warping algorithm %J Integration %K vlsi %V 4 %N 2 %D June 1986 %P 155-174 %A H.C. Card %A W. Pries %A R.D, McLeod %T Contributions to VLSI computational complexity theory from bounds on current density %J Integration %K vlsi %V 4 %N 2 %D June 1986 %P 175-184 %A J.G. Rathnell %T Information flow in VLSI design %J Integration %K vlsi %V 4 %N 2 %D June 1986 %P 185-192 %A Emile H.L. Aarts %A Frans M.J. de\ Bont %A Erik H.A. Habers %A Peter J.M. van\ Laarhoven %T Parallel implementations of the statistical cooling algorithm %J Integration %K vlsi %V 4 %N 3 %D September 1986 %P 209-238 %A L.G. Chen %A J.Y. Lee %A J.F. Wang %A K.T. Chen %T Fast execution for circuit consistency verification %J Integration %K vlsi %V 4 %N 3 %D September 1986 %P 239-262 %A Magdy A. Bayoumi %T Lower bounds for VLSI implementation of residue number system architectures %J Integration %K vlsi %V 4 %N 3 %D September 1986 %P 263-269 %A Bruce Char %T Computer algebra and logic programming %J Integration %K vlsi %V 4 %N 3 %D September 1986 %P 271-274 %A D.F. Wong %A C.L. Liu %T Compacted channel routing with via placement restrictions %J Integration %K vlsi %V 4 %N 4 %D December 1986 %P 287-307 %A T. Lengauer %A S. Naher %T An analysis of ternary simulation as a tool for race detection in digital MOS circuits %J Integration %K vlsi %V 4 %N 4 %D December 1986 %P 309-330 %A Sergio Brofferio %A Michele Taliercio %T PLA implementation of a differential predictive coder for digital television signals %J Integration %K vlsi %V 4 %N 4 %D December 1986 %P 331-343 %A S. Chowdhury %A M.A. Breuer %T An O(n) algorithm for width determination of power-ground routes for VLSI circuits %J Integration %K vlsi %V 4 %N 4 %D December 1986 %P 345-355 %A E. Shragowitz %A S. Keel %T A global router based on a multicommodity flow model %J Integration %K vlsi %V 5 %N 1 %D March 1987 %P 3-16 %A H.W. Leong %A C.L. Liu %T Algorithms for permutation channel routing %J Integration %K vlsi %V 5 %N 1 %D March 1987 %P 17-45 %A A.S. Shubat %A J.A. Pretorius %A C.A.T. Salama %T Expandable arithmetic block macrocell %J Integration %K vlsi %V 5 %N 1 %D March 1987 %P 47-71 %A Tao Li %T SYSIM: a simulation tool for systolic processors %J Integration %K vlsi %V 5 %N 1 %D March 1987 %P 73-76 %A B. Codenotti %A F. Romani %T A compact and modular VLSI design for the solution of general sparse linear systems %J Integration %K vlsi %V 5 %N 1 %D March 1987 %P 77-86 %A J.A. Brzozowski %A M. Yoeli %T Combinational static CMOS networks %J Integration %K vlsi %V 5 %N 2 %D June 1987 %P 103-122 %A Mark Greentstreet %A Peter Moller-Nielsen %A Jorgen Staunstrup %T VLSI with a very low scale investment %J Integration %K vlsi %V 5 %N 2 %D June 1987 %P 125-132 %K Aarhus NORCHIP %A Krzysztof Kuchcinski %A Zebo Peng %T Microprogramming implementation of timed Petri nets %J Integration %K vlsi %V 5 %N 2 %D June 1987 %P 133-144 %A Tony Larsson %T Semantics of a hardware specification language and related transformation rules %J Integration %K vlsi %V 5 %N 2 %D June 1987 %P 145-158 %A B. Sikstrom %A L. Wanhammar %A M. Afghani %A J. Pencz %T A high speed 2-D discrete cosine transform chip %J Integration %K vlsi %V 5 %N 2 %D June 1987 %P 159-169 %A Olli Vainio %A Pekka Heinonen %A Yrjo Neuvo %T Integrated FIR median hybrid filter %J Integration %K vlsi %V 5 %N 2 %D June 1987 %P 171-177