%A Hillel Ofek
%T Design automation
%J IEEE Design & Test of Computers
%K ieee_dt
%V 1
%N 1
%D February 1984
%P 16-17

%A Francine S. Frome
%T Improving color CAD systems for users:
some suggestions from human factors studies
%J IEEE Design & Test of Computers
%K ieee_dt
%V 1
%N 1
%D February 1984
%P 18-29

%A Larry N. Dunn
%T IBM's engineering design system support for VLSI design and verification
%J IEEE Design & Test of Computers
%K ieee_dt
%V 1
%N 1
%D February 1984
%P 30-43

%A Charles W. Rose
%A Greg M. Ordy
%A Paul J. Drongowski
%T N.mPc: a study in university-industry technology transfer
%J IEEE Design & Test of Computers
%K ieee_dt
%V 1
%N 1
%D February 1984
%P 44-59

%A Thaddeus J. Kowalski
%A Donald E. Thomas
%T The VLSI design automation assistant: an IBM System/370 design
%J IEEE Design & Test of Computers
%K ieee_dt
%V 1
%N 1
%D February 1984
%P 60-70

%A Zeev Barzilai
%A Leendert M. Huisman
%A Gabrial M. Silberman
%A Donald T. Tang
%A Lin S. Woo
%T Fast pass-transistor simulation for custom MOS circuits
%J IEEE Design & Test of Computers
%K ieee_dt
%V 1
%N 1
%D February 1984
%P 71-82

%A Miron Abramovici
%A P.R. Menon
%A David T. Miller
%T Critical path tracing: an alternative to fault simulation
%J IEEE Design & Test of Computers
%K ieee_dt
%V 1
%N 1
%D February 1984
%P 83-93

%A Robert E. Anderson
%T Linking design and test
%J IEEE Design & Test of Computers
%K ieee_dt
%V 1
%N 2
%D May 1984
%P 27-32

%A John P. Kuban
%A William C. Bruce
%T Self-testing the Motorola MC6804P2
%J IEEE Design & Test of Computers
%K ieee_dt
%V 1
%N 2
%D May 1984
%P 33-41

%A William S. Blackley
%A Mervyn A. Jack
%A James R. Jordan
%T A digital polarity correlator with built-in self test and self repair
%J IEEE Design & Test of Computers
%K ieee_dt
%V 1
%N 2
%D May 1984
%P 42-51

%A Nikos Kanopoulos
%A G. Thomas Mitchell
%T Design for testability and self-testing approaches
for bit-serial signal processors
%J IEEE Design & Test of Computers
%K ieee_dt
%V 1
%N 2
%D May 1984
%P 52-60

%A Robert C. Kroeger
%T Testability emphasis in the General Electric A/VLSI program
%J IEEE Design & Test of Computers
%K ieee_dt
%V 1
%N 2
%D May 1984
%P 61-67

%A Chantal Robach
%A Philippe Malecha
%A Gilles Michel
%T CATA: a computer-aided test analysis system
%J IEEE Design & Test of Computers
%K ieee_dt
%V 1
%N 2
%D May 1984
%P 68-82

%A Michael J. Bending
%T Hitest: a knowledge-based test generation system
%J IEEE Design & Test of Computers
%K ieee_dt
%V 1
%N 2
%D May 1984
%P 83-93

%A David Florcik
%A David Low
%A Martin Roche
%T Prototype debug using ATE
%J IEEE Design & Test of Computers
%K ieee_dt
%V 1
%N 2
%D May 1984
%P 94-100

%A Rudy Garcia
%T The Fairchild Sentry 50 tester: establishing new ATE performance limits
%J IEEE Design & Test of Computers
%K ieee_dt
%V 1
%N 2
%D May 1984
%P 101-109

%A Richard M. Sednak
%A Donald E. Thomas
%T Design and test - probing the state of the art
%J IEEE Design & Test of Computers
%K ieee_dt
%V 1
%N 3
%D August 1984
%P 18-20

%A Tom Blank
%T A survey of hardware accelerators used in computer-aided design
%J IEEE Design & Test of Computers
%K ieee_dt
%V 1
%N 3
%D August 1984
%P 21-42

%A W.R. Heller
%A C. George Hsi
%A Wadie F. Mikhail
%T Wirability - designing wiring space for chips and chip packages
%J IEEE Design & Test of Computers
%K ieee_dt
%V 1
%N 3
%D August 1984
%P 43-51

%A Jim H. Kim
%A John McDermott
%A Daniel P. Siewiorek
%T Exploiting domain knowledge in IC cell layout
%J IEEE Design & Test of Computers
%K ieee_dt
%V 1
%N 3
%D August 1984
%P 52-65

%A Ronald L. Wadsack
%T Design verification and testing the WE 32100 CPUs
%J IEEE Design & Test of Computers
%K ieee_dt
%V 1
%N 3
%D August 1984
%P 66-75

%A Prithviraj Banerjee
%A Jacob A. Abraham
%T Characterization and testing of physical failures in MOS logic circuits
%J IEEE Design & Test of Computers
%K ieee_dt
%V 1
%N 3
%D August 1984
%P 76-89

%A Mark R. Barber
%T Fundamental timing problems in testing MOS VLSI on modern ATE
%J IEEE Design & Test of Computers
%K ieee_dt
%V 1
%N 3
%D August 1984
%P 90-98

%A Gordon E. Moore
%T A macro view of microelectronics (interview)
%J IEEE Design & Test of Computers
%K ieee_dt
%V 1
%N 4
%D November 1984
%P 15-24

%A Akira Motohara
%A Hideo Fujiwara
%T Design for testability for complete test coverage
%J IEEE Design & Test of Computers
%K ieee_dt
%V 1
%N 4
%D November 1984
%P 25-32

%A Steve Sapiro
%T The electronic workstation - an overview
%J IEEE Design & Test of Computers
%K ieee_dt
%V 1
%N 4
%D November 1984
%P 33-44

%A Johnny J. LeBlanc
%T LOCST: a built-in self-test technique
%J IEEE Design & Test of Computers
%K ieee_dt
%V 1
%N 4
%D November 1984
%P 45-52

%A Dwight D. Hill
%T Icon: a tool for design at schematic, virtual grid, and layout levels
%J IEEE Design & Test of Computers
%K ieee_dt
%V 1
%N 4
%D November 1984
%P 53-61

%A Yashwant K. Malaiya
%A Ramesh Narayanaswamy
%T Modeling and testing for timing faults in synchronous sequential circuits
%J IEEE Design & Test of Computers
%K ieee_dt
%V 1
%N 4
%D November 1984
%P 62-74

%A Alice C. Parker
%T Automated synthesis of digital systems
%J IEEE Design & Test of Computers
%K ieee_dt
%V 1
%N 4
%D November 1984
%P 75-81

%A Lawrence A. O'Neill
%T Design automation
%J IEEE Design & Test of Computers
%K ieee_dt
%V 2
%N 1
%D February 1985
%P 16-18

%A John K. Ousterhout
%A Gordon T. Hamachi
%A Robert N. Mayo
%A Walter S. Scott
%A George S. Taylor
%T The Magic VLSI layout system
%J IEEE Design & Test of Computers
%K ieee_dt
%V 2
%N 1
%D February 1985
%P 19-30

%A Todd J. Wagner
%T Hierarchical layout verification
%J IEEE Design & Test of Computers
%K ieee_dt
%V 2
%N 1
%D February 1985
%P 31-37

%A Sunil K. Jan
%A Wishwani D. Agrawal
%T Statistical fault analysis
%J IEEE Design & Test of Computers
%K ieee_dt
%V 2
%N 1
%D February 1985
%P 38-44

%A Louis I. Steinberg
%A Tom M. Mitchell
%T The Redesign system: a knowledge-based approach to VLSI CAD
%J IEEE Design & Test of Computers
%K ieee_dt
%V 2
%N 1
%D February 1985
%P 45-54

%A Karl J. Lieberherr
%T Toward a standard hardware description language
%J IEEE Design & Test of Computers
%K ieee_dt
%V 2
%N 1
%D February 1985
%P 55-62

%A John D. Crawford
%T EDIF: a mechanism for the exchange of design data
%J IEEE Design & Test of Computers
%K ieee_dt
%V 2
%N 1
%D February 1985
%P 63-69

%A Richard M. Sedmak
%T Built-in self test: pass or fail ?
%J IEEE Design & Test of Computers
%K ieee_dt
%V 2
%N 2
%D April 1985
%P 17-20

%A Edward J. McCluskey
%T Built-in self-test techniques
%J IEEE Design & Test of Computers
%K ieee_dt
%V 2
%N 2
%D April 1985
%P 21-28

%A Edward J. McCluskey
%T Built-in self-test structures
%J IEEE Design & Test of Computers
%K ieee_dt
%V 2
%N 2
%D April 1985
%P 29-36

%A Robert Trewer
%A Hideo Fujiwara
%A Vinod K. Agarwal
%T Implementing a built-in self-test PLA design
%J IEEE Design & Test of Computers
%K ieee_dt
%V 2
%N 2
%D April 1985
%P 37-49

%A Rochard J. Illman
%T Self-tested data flow logic: a new approach
%J IEEE Design & Test of Computers
%K ieee_dt
%V 2
%N 2
%D April 1985
%P 50-58

%A Thomas W. Williams
%T Test length in a self-testing environment
%J IEEE Design & Test of Computers
%K ieee_dt
%V 2
%N 2
%D April 1985
%P 59-63

%A R. Gary Daniels
%A William C. Bruce
%T Built-in self-test trends in Motorola microprocessors
%J IEEE Design & Test of Computers
%K ieee_dt
%V 2
%N 2
%D April 1985
%P 64-74

%A Carolyn E. Tajnai
%T Fred Ternan, the father of Silicon Valley
%J IEEE Design & Test of Computers
%K ieee_dt
%V 2
%N 2
%D April 1985
%P 75-81

%A Donald L. Lacy
%A Lawrence A. Drenan
%T Implementing and managing a CAD system based on vendor-supplied tools
%J IEEE Design & Test of Computers
%K ieee_dt
%V 2
%N 2
%D April 1985
%P 82-87

%A John P. Hayes
%T Fault modeling
%J IEEE Design & Test of Computers
%K ieee_dt
%V 2
%N 2
%D April 1985
%P 88-95

%A Peter Bronecke
%T The economics of test
%J IEEE Design & Test of Computers
%K ieee_dt
%V 2
%N 3
%D June 1985
%P 18-19

%A G.H. Bowers
%A B.G. Pratt
%T Low-cost testers: are they really low cost ?
%J IEEE Design & Test of Computers
%K ieee_dt
%V 2
%N 3
%D June 1985
%P 20-28

%A Anthony P. van\ der\ Heuvel
%A Noshir F. Khory
%T A basis for setting burn-in yield criteria
%J IEEE Design & Test of Computers
%K ieee_dt
%V 2
%N 3
%D June 1985
%P 29-34

%A John R. Day
%T A fault-driven comprehensive redundancy program
%J IEEE Design & Test of Computers
%K ieee_dt
%V 2
%N 3
%D June 1985
%P 35-44

%A Dean Bandes
%T Exploratory data analysis for semiconductor manufacturing
%J IEEE Design & Test of Computers
%K ieee_dt
%V 2
%N 3
%D June 1985
%P 45-55

%A Douglas K. Shirachi
%T Codec testing using synchronized analog and digital signals
%J IEEE Design & Test of Computers
%K ieee_dt
%V 2
%N 3
%D June 1985
%P 56-63

%A Thomas G. Szymanski
%A Christopher J. Van\ Wyk
%T Goalie: a space efficient system for VLSI artwork analysis
%J IEEE Design & Test of Computers
%K ieee_dt
%V 2
%N 3
%D June 1985
%P 64-72

%A B.R. Inman
%T Design and test in the private sector (interview)
%J IEEE Design & Test of Computers
%K ieee_dt
%V 2
%N 3
%D June 1985
%P 73-80

%A Donald Thomas
%T Artificial intelligence in design and test
%J IEEE Design & Test of Computers
%K ieee_dt
%V 2
%N 4
%D August 1985
%P 21

%A Aart J. de\ Geus
%A William Cohen
%T A rule-based expert system for optimizing combinational logic
%J IEEE Design & Test of Computers
%K ieee_dt
%V 2
%N 4
%D August 1985
%P 22-32

%A T.J. Kowalski
%A D.J. Geiger
%A W.H. Wolf
%A W. Fichtner
%T The VLSI design automation assistant: from algorithms to silicon
%J IEEE Design & Test of Computers
%K ieee_dt
%V 2
%N 4
%D August 1985
%P 33-43

%A Robert A. Mueller
%A Josephn Varghese
%T Knowledge-based code selection methods in retargetable microcode synthesis
%J IEEE Design & Test of Computers
%K ieee_dt
%V 2
%N 4
%D August 1985
%P 44-55

%A Magdy S. Abadir
%A Melvin A. Breuer
%T A knowledge-based system for designing testable VLSI chips
%J IEEE Design & Test of Computers
%K ieee_dt
%V 2
%N 4
%D August 1985
%P 56-68

%A A. Jesse Wilkinson
%T MIND: an inside look at an expert system for electronic diagnosis
%J IEEE Design & Test of Computers
%K ieee_dt
%V 2
%N 4
%D August 1985
%P 69-77

%A Tariq Samad
%A Stephen W. Director
%T Natural-language interface for CAD - a first step
%J IEEE Design & Test of Computers
%K ieee_dt
%V 2
%N 4
%D August 1985
%P 78-86

%A Akihiko Yamada
%T Design and test in Japan
%J IEEE Design & Test of Computers
%K ieee_dt
%V 2
%N 5
%D October 1985
%P 15-16

%A O. Karatsu
%A T. Hoshino
%A M. Endo
%A H. Kitazawa
%A T. Adachi
%A K. Ueda
%T An integrated design automation system for VLSI circuits
%J IEEE Design & Test of Computers
%K ieee_dt
%V 2
%N 5
%D October 1985
%P 17-26

%A Takao Uehara
%T A knowledge-based logic design system
%J IEEE Design & Test of Computers
%K ieee_dt
%V 2
%N 5
%D October 1985
%P 27-34

%A Kiyoshi Enomoto
%A Sunichiro Nakamura
%A Takuji Ogihara
%A Shinichi Murai
%T LORES-2: a logic reorganization system
%J IEEE Design & Test of Computers
%K ieee_dt
%V 2
%N 5
%D October 1985
%P 35-42

%A Tokinori Kozawa
%A Hidekaza Terai
%T Research in design automation for VLSI layout
%J IEEE Design & Test of Computers
%K ieee_dt
%V 2
%N 5
%D October 1985
%P 43-53

%A Shigehiro Funatsu
%A Masato Kawai
%T An automatic test-generation system for large digital circuits
%J IEEE Design & Test of Computers
%K ieee_dt
%V 2
%N 5
%D October 1985
%P 54-60

%A Nobuhiko Koike
%A Kenji Ohmori
%A Tohru Sasaki
%T HAL: a high-speed logic simulation machine
%J IEEE Design & Test of Computers
%K ieee_dt
%V 2
%N 5
%D October 1985
%P 61-73

%A Norio Kuji
%A Teruo Tanama
%A Takao Yano
%T A fully automated electron-beam test system for VLSI circuits
%J IEEE Design & Test of Computers
%K ieee_dt
%V 2
%N 5
%D October 1985
%P 74-82

%A Tohru Kazamaki
%T Milestones of new-generation ATE
%J IEEE Design & Test of Computers
%K ieee_dt
%V 2
%N 5
%D October 1985
%P 83-89

%A Tohru Moto-Oka
%T The Japanese Fifth-Generation Computer Systems project (interview)
%J IEEE Design & Test of Computers
%K ieee_dt
%V 2
%N 5
%D October 1985
%P 90-99

%A Jack Arabian
%T The path to successful production
%J IEEE Design & Test of Computers
%K ieee_dt
%V 2
%N 6
%D December 1985
%P 11-12

%A John P. Shen
%A W. Maly
%A F. Joel Ferguson
%T Inductive fault analysis of MOS integrated circuits
%J IEEE Design & Test of Computers
%K ieee_dt
%V 2
%N 6
%D December 1985
%P 13-26

%A Peter Odryna
%A Andrzej J. Strojwas
%T PROD: a VLSI fault diagnosis system
%J IEEE Design & Test of Computers
%K ieee_dt
%V 2
%N 6
%D December 1985
%P 27-35

%A Kofi E. Torku
%A Dave A. Kiesling
%T Noise problems in testing VLSI hardware
%J IEEE Design & Test of Computers
%K ieee_dt
%V 2
%N 6
%D December 1985
%P 36-43

%A Tim Moore
%A Stephen Garner
%T Autoprobing on the L200 functional tester
%J IEEE Design & Test of Computers
%K ieee_dt
%V 2
%N 6
%D December 1985
%P 44-49

%A David F. Farnholtz
%T Operational life testing of electronic components
%J IEEE Design & Test of Computers
%K ieee_dt
%V 2
%N 6
%D December 1985
%P 50-56

%A Wayne Ponik
%T Teradyne's J967 VLSI test system: getting VLSI to the market on time
%J IEEE Design & Test of Computers
%K ieee_dt
%V 2
%N 6
%D December 1985
%P 57-62

%A Anon
%T Gate-level simulation (tutorial)
%J IEEE Design & Test of Computers
%K ieee_dt
%V 2
%N 6
%D December 1985
%P 63-71

%A Prathima Agrawal
%T Sampling quality
%J IEEE Design & Test of Computers
%K ieee_dt
%V 3
%N 1
%D February 1986
%P 10-11

%A Rostam Joobbani
%A Daniel P. Siowiorek
%T WEAVER: a knowledge-based routing expert
%J IEEE Design & Test of Computers
%K ieee_dt
%V 3
%N 1
%D February 1986
%P 12-23

%A Walter S. Scott
%A John K. Ousterhout
%T Magic's circuit extractor
%J IEEE Design & Test of Computers
%K ieee_dt
%V 3
%N 1
%D February 1986
%P 24-34

%A Andrzej J. Strojwas
%T The CMU-CAD system
%J IEEE Design & Test of Computers
%K ieee_dt
%V 3
%N 1
%D February 1986
%P 35-44

%A H.S. Fung
%A S. Hirschhorn
%T An automatic DFT system for the Silc silicon compiler
%J IEEE Design & Test of Computers
%K ieee_dt
%V 3
%N 1
%D February 1986
%P 45-57

%A Anshul Kumar
%A Anjali Arya
%A V.V. Swaminathan
%A Amit Misra
%T Automatic generation of digital system schematic diagrams
%J IEEE Design & Test of Computers
%K ieee_dt
%V 3
%N 1
%D February 1986
%P 58-65

%A Louis K. Scheffer
%A Ronny Soetarman
%T Hierarchical analysis of IC artwork with user-defined rules
%J IEEE Design & Test of Computers
%K ieee_dt
%V 3
%N 1
%D February 1986
%P 66-74

%A C. Durward Rogers
%T The VIVID symbolic design system: current overview and future directions
%J IEEE Design & Test of Computers
%K ieee_dt
%V 3
%N 1
%D February 1986
%P 75-81

%A Ron Waxman
%T The VHSIC hardware description language - a glimpse of the future
%J IEEE Design & Test of Computers
%K ieee_dt
%V 3
%N 2
%D April 1986
%P 10-11
%K VHDL HDL

%A Allen Dewey
%A Anthony Gadient
%T VHDL motivation
%J IEEE Design & Test of Computers
%K ieee_dt
%V 3
%N 2
%D April 1986
%P 12-16

%A J.H. Aylor
%A R. Waxman
%A C. Scarratt
%T VHDL - feature description and analysis
%J IEEE Design & Test of Computers
%K ieee_dt
%V 3
%N 2
%D April 1986
%P 17-27
%K IDL, TI-HDL, CDL, AHPL, ZEUS, CONLAN, TEGAS, ISPS

%A Roger Lipsett
%A Erich Marschner
%T VHDL - the language
%J IEEE Design & Test of Computers
%K ieee_dt
%V 3
%N 2
%D April 1986
%P 28-41

%A Alfred S. Gilman
%T VHDL - the designer environment
%J IEEE Design & Test of Computers
%K ieee_dt
%V 3
%N 2
%D April 1986
%P 42-47

%A Al Lowenstein
%A Greg Winter
%T VHDL's impact on test
%J IEEE Design & Test of Computers
%K ieee_dt
%V 3
%N 2
%D April 1986
%P 48-53

%A J.D. Nash
%A L.F. Sanders
%T VHDL critique
%J IEEE Design & Test of Computers
%K ieee_dt
%V 3
%N 2
%D April 1986
%P 54-65

%A W.R. Simpson
%A C.S. Dowling
%T WRAPLE: the weighted repair assistance program learning extensions
%J IEEE Design & Test of Computers
%K ieee_dt
%V 3
%N 2
%D April 1986
%P 66-73

%A Dave W. Palmer
%A John A. Wisniewski
%T IC design capability conversion from mainframe to workstation environment
%J IEEE Design & Test of Computers
%K ieee_dt
%V 3
%N 3
%D June 1986
%P 18-24

%A Mark A. Liston
%T Benchmarking engineering workstations
%J IEEE Design & Test of Computers
%K ieee_dt
%V 3
%N 3
%D June 1986
%P 25-30

%A Rolf-Dieter Fiebrich
%T A supercomputer workstation for VLSI CAD
%J IEEE Design & Test of Computers
%K ieee_dt
%V 3
%N 3
%D June 1986
%P 31-37

%A Akira Sugimoto
%T YEGA: a visual modeling language for digital systems
%J IEEE Design & Test of Computers
%K ieee_dt
%V 3
%N 3
%D June 1986
%P 38-45

%A K.I. Konandopani
%A Edward J. McGrath
%T A wirelist compare program for verifying VLSI layouts
%J IEEE Design & Test of Computers
%K ieee_dt
%V 3
%N 3
%D June 1986
%P 46-51

%A Dilip K. Bhavsar
%T A new economical implementation for scannable flip-flops in MOS
%J IEEE Design & Test of Computers
%K ieee_dt
%V 3
%N 3
%D June 1986
%P 52-56

%A Wayne Wolf
%T Sticks compaction and assembly
%J IEEE Design & Test of Computers
%K ieee_dt
%V 3
%N 3
%D June 1986
%P 57-63

%A Thirumalai Sridhar
%T A new parallel test approach for large memories
%J IEEE Design & Test of Computers
%K ieee_dt
%V 3
%N 4
%D August 1986
%P 15-22

%A Teruo Tamama
%A Norio Kuji
%T Integrating an electron-beam system into VLSI fault diagnosis
%J IEEE Design & Test of Computers
%K ieee_dt
%V 3
%N 4
%D August 1986
%P 23-32

%A Dennis Petrich
%T Achieving accurate timing measurements on TTL/CMOS devices
%J IEEE Design & Test of Computers
%K ieee_dt
%V 3
%N 4
%D August 1986
%P 33-42

%A M. Abramovici
%A J.J. Kulikowski
%A P.R. Menon
%A D.T. Miller
%T SMART and FAST: test generation for VLSI scan-design circuits
%J IEEE Design & Test of Computers
%K ieee_dt
%V 3
%N 4
%D August 1986
%P 43-55

%A Jerry M. Soden
%A Charles F. Hawkins
%T Test considerations for gate oxide shorts in CMOS ICs
%J IEEE Design & Test of Computers
%K ieee_dt
%V 3
%N 4
%D August 1986
%P 56-64

%A Kenneth P. Parker
%T Testability: barriers to acceptance
%J IEEE Design & Test of Computers
%K ieee_dt
%V 3
%N 5
%D October 1986
%P 11-16

%A Madhukar K. Reddy
%A Sudhakar M. Reddy
%T Detecting FET stuck-open faults in CMOS latches and flip-flops
%J IEEE Design & Test of Computers
%K ieee_dt
%V 3
%N 5
%D October 1986
%P 17-26

%A Sunil K. Jain
%A Charles E. Stroud
%T Built-in self-testing on embedded memories
%J IEEE Design & Test of Computers
%K ieee_dt
%V 3
%N 5
%D October 1986
%P 27-38

%A E.T. Grinthal
%T Software quality assurance and CAD user interfaces
%J IEEE Design & Test of Computers
%K ieee_dt
%V 3
%N 5
%D October 1986
%P 39-48

%A David Hightowert
%A Aart de\ Geus
%A Patrick Fasang
%A Robert Griffin
%A Gary Leive
%T Computer-aided-design research at the GE Microelectronics Center
%J IEEE Design & Test of Computers
%K ieee_dt
%V 3
%N 5
%D October 1986
%P 49-56

%A H. de\ Man
%A J. rabaey
%A L. Claesen
%T Cathedral-II: a silicon compiler for digital signal processing
%J IEEE Design & Test of Computers
%K ieee_dt
%V 3
%N 6
%D December 1986
%P 13-25

%A F.P.M. Beenker
%A J.K.E. Eerdewijk
%A R.B.W. Gerritsen
%A F.N. Peacock
%A M. van\ der\ Star
%T Macro testing: unifying IC and board test
%J IEEE Design & Test of Computers
%K ieee_dt
%V 3
%N 6
%D December 1986
%P 26-34

%A J.P. Mucha
%A W. Daehn
%A J. Gross
%T Self-test in a standard cell environment
%J IEEE Design & Test of Computers
%K ieee_dt
%V 3
%N 6
%D December 1986
%P 35-42

%A Hassan K. Reghbati
%T Fault detection in PLAs
%J IEEE Design & Test of Computers
%K ieee_dt
%V 3
%N 6
%D December 1986
%P 43-51

%A Randy H. Katz
%A Rajiv Bhateja
%A Ellis E-Li Chang
%A David Gedye
%A Vony Trijanto
%T Design version management
%J IEEE Design & Test of Computers
%K ieee_dt
%V 4
%N 1
%D February 1987
%P 12-22

%A Sy-Yen Kuo
%A W. Kent Fuchs
%T Efficient spare allocation for reconfigurable arrays
%J IEEE Design & Test of Computers
%K ieee_dt
%V 4
%N 1
%D February 1987
%P 24-31

%A Hiroyuki Watanabe
%A Bryan Ackland
%T Flute: an expert floor planner for full-custom VLSI design
%J IEEE Design & Test of Computers
%K ieee_dt
%V 4
%N 1
%D February 1987
%P 32-41

%A Kewal K. Saluja
%A Siew H. Sng
%A Kozo Kinoshita
%T Built-in self-testing RAM: apractical alternative
%J IEEE Design & Test of Computers
%K ieee_dt
%V 4
%N 1
%D February 1987
%P 42-51

%A Sudhakar M. Reddy
%A R. Dabdapani
%T Scan design using standard flip-flops
%J IEEE Design & Test of Computers
%K ieee_dt
%V 4
%N 1
%D February 1987
%P 52-54

%A Steve Kang
%T Physical design of microprocessors
%J IEEE Design & Test of Computers
%K ieee_dt
%V 4
%N 3
%D June 1987
%P 10-11

%A David R. Ditzel
%A Alan D. Berenbaum
%T Using CAD in the design of CRISP
%J IEEE Design & Test of Computers
%K ieee_dt
%V 4
%N 3
%D June 1987
%P 21-31
%K ATT

%A H.H. Chao
%A S. Ong
%A M. Tsai
%A F.W. Shih
%A K.W. Lewis
%A J.Y.F. Tang
%A C.A. Trempel
%A H.N. Yu
%A P.E. McCormick
%A C.V. Davis,\ Jr.
%A A.L. Diamond
%A T.J. Medve
%A J.C.L. Hou
%T Designing the Micro/370
%J IEEE Design & Test of Computers
%K ieee_dt
%V 4
%N 3
%D June 1987
%P 32-40
%K IBM

%A Patrick P. Gelsinger
%T Design and test of the 80386
%J IEEE Design & Test of Computers
%K ieee_dt
%V 4
%N 3
%D June 1987
%P 42-50
%K Intel

%A Shoji Horiguchi
%A Hiroshi Yoshimura
%A Mitsuyoshi Nagatani
%A Kennosuke Fukami
%T The design of dedicated 32-bit processors
%J IEEE Design & Test of Computers
%K ieee_dt
%V 4
%N 3
%D June 1987
%P 52-58

%A John P. Shen
%A Sandy Hirschhorn
%T Switch-level techniques
%J IEEE Design & Test of Computers
%K ieee_dt
%V 4
%N 4
%D August 1987
%P 15-16

%A John P. Hayes
%T An introduction to switch-level modeling
%J IEEE Design & Test of Computers
%K ieee_dt
%V 4
%N 4
%D August 1987
%P 18-25

%A Randal E. Bryant
%T A survey of switch-level algorithms
%J IEEE Design & Test of Computers
%K ieee_dt
%V 4
%N 4
%D August 1987
%P 26-40

%A DIck L. Liu
%A Edward J. McCluskey
%T Designing CMOS circuits for switch-level testability
%J IEEE Design & Test of Computers
%K ieee_dt
%V 4
%N 4
%D August 1987
%P 42-49

%A Kit Yoke Tham
%T Parallel processing of CAD applications
%J IEEE Design & Test of Computers
%K ieee_dt
%V 4
%N 5
%D October 1987
%P 13-17

%A Frederica Darema
%A Gregory F. Pfister
%T Multipurpose parallelism for VLSI CAD on the RP3
%J IEEE Design & Test of Computers
%K ieee_dt
%V 4
%N 5
%D October 1987
%P 19-27
%K IBM, Epex

%A P. Agrawal
%A W.J. Dally
%A W.C. Fischer
%A H.V. Jagadish
%A A.S. Krishnakumar
%A R. Tutudjian
%T MARS: a multiprocessor-based programmable accelerator
%J IEEE Design & Test of Computers
%K ieee_dt
%V 4
%N 5
%D October 1987
%P 28-37

%A Thomas Ryan
%A Edwin Rogers
%T An ISMA Lee router accelerator
%J IEEE Design & Test of Computers
%K ieee_dt
%V 4
%N 5
%D October 1987
%P 38-45
%K iterative stater machine arrays