%A David L. Budde %A Steven R. Colley %A Stephen L. Domenik %A Allan L. Goodman %A James D. Howard %A Michael T. Imel %T The execution unit for the VLSI 432 general data processor %J IEEE Journal of Solid-State Circuits %K ieee_jssc %V SC-16 %N 5 %D October 1981 %P 514-521 %K Intel iAPX iAPX-432 %A John A. Bayliss %A John A. Deetz %A Chun-Kit Ng %A Scott A. Ogilvie %A Craig B. Peterson %A Doran K. Wilde %T The interpace processor for the Intel VLSI 432 32-bit computer %J IEEE Journal of Solid-State Circuits %K ieee_jssc %V SC-16 %N 5 %D October 1981 %P 522-530 %K Intel iAPX iAPX-432 %A John A. Bayliss %A Steven R. Colley %A Roy H. Krawitz %A Gary A. McCormick %A William S. Richardson %A Doran K. Wilde %A Leon L. Wittmer %T The instruction decoding unit for the VLSI 432 general data processor %J IEEE Journal of Solid-State Circuits %K ieee_jssc %V SC-16 %N 5 %D October 1981 %P 531-537 %K Intel iAPX iAPX-432 %A Joseph W. Beyers %A Louis J. Dohse %A Joseph P. Fucetola %A Richard L. Kochis %A Clifford G. Lob %A Gary L. Taylor %A Eugene R. Zeller %T A 32-bit VLSI CPU chip %J IEEE Journal of Solid-State Circuits %K ieee_jssc %V SC-16 %N 5 %D October 1981 %P 537-542 %K Hewlett-Packard Focus %A James M. Mikkelson %A Lawrence A. Hall %A Arun K. Malhotra %A S. Dana Seccombe %A Martin S. Wilson %T An NMOS VLSI process for fabrication of a 32-bit CPU chip %J IEEE Journal of Solid-State Circuits %K ieee_jssc %V SC-16 %N 5 %D October 1981 %P 542-547 %K Hewlett-Packard Focus %A Asher Kaminker %A Leslie Kohn %A Yoav Lavi %A Avraham Menachem %A Zvi Soha %T A 32-bit microprocessor with virtual memory support %J IEEE Journal of Solid-State Circuits %K ieee_jssc %V SC-16 %N 5 %D October 1981 %P 548-557 %K National Semiconductor Natsemi 16032 NS16032 %A Larry F. Childs %A Ryan T. Hirose %T An 18ns 4K*4 CMOS SRAM %J IEEE Journal of Solid-State Circuits %K ieee_jssc %V SC-19 %N 5 %D October 1984 %P 545-551 %A Nobumichi Okazaki %A Takaaki Komatsu %A Naoya Hoshi %A Kunihiko Tsuboi %A Takashi Shimada %T A 16ns 2K*8 bit full CMOS SRAM %J IEEE Journal of Solid-State Circuits %K ieee_jssc %V SC-19 %N 5 %D October 1984 %P 552-556 %A Jun-Ichi Miyamoto %A Shinji Saito %A Hiroshi Momose %A Hideki Shibata %A Koichi Kanzaki %A Tetsuya Iizuka %T A high-speed 64K CMOS RAM with bipolar sense amplifiers %J IEEE Journal of Solid-State Circuits %K ieee_jssc %V SC-19 %N 5 %D October 1984 %P 557-563 %A Stanley E. Schuster %A Barbara Chappell %A Victor di\ Lonardo %A Peter E. Britton %T A 20ns 64K (4K*16) NMOS RAM %J IEEE Journal of Solid-State Circuits %K ieee_jssc %V SC-19 %N 5 %D October 1984 %P 564-571 %A Takashi Yamanaka %A Shigeru Koshimaru %A Osamu Kudoh %A Yakashi Ozawa %A Nobuyuki Yasuoka %A Hiroshi Asai %A Nobuyuki Harashima %A Shinichi Kikuchi %T A 25ns 64K static RAM %J IEEE Journal of Solid-State Circuits %K ieee_jssc %V SC-19 %N 5 %D October 1984 %P 572-577 %A Takayasu Sakurai %A Junichi Matsunaga %A Mitsuo Isobe %A Takayuki Ohtani %A Kazuhiro Sawada %A Akira Aono %A Hiroshi Nozawa %A Tetsuya Iizuka %A Susumu Kohyama %T A low power 46ns 256 kbit CMOS static RAM with dynamic double word line %J IEEE Journal of Solid-State Circuits %K ieee_jssc %V SC-19 %N 5 %D October 1984 %P 578-585 %A Robert A. Kertis %A Kelly J. Fitzpatrick %A Kul B. Ohri %T A 60ns 256K*1 bit DRAM using LD3 technology and double-level metal interconnection %J IEEE Journal of Solid-State Circuits %K ieee_jssc %V SC-19 %N 5 %D October 1984 %P 585-590 %A Koichiro Mashiko %A Toshifumi Kobayashi %A Hiroshi Miyamoto %A Kazutami Arimoto %A Yoshikazu Morooka %A Masahiro Hatanaka %A Michihiro Yamada %A Takao Nakano %T A 70ns 256K DRAM with bit-line shield %J IEEE Journal of Solid-State Circuits %K ieee_jssc %V SC-19 %N 5 %D October 1984 %P 591-596 %A Dieter Kantz %A Jurgen R. Goetz %A Regine Bender %A Manfred Bahring %A Jurgen Wawersig %A Willibald Meyer %A Wolfgang Muller %T A 256K DRAM with descrambled redundancy test capability %J IEEE Journal of Solid-State Circuits %K ieee_jssc %V SC-19 %N 5 %D October 1984 %P 596-602 %A Erich K. Baier %A Rainer Clemen %A Werner Haug %A Walter Fischer %A Rolf Mueller %A Wolf Dieter Loehlein %A Horst Barsuhn %T A fast 256K DRAM designed for a wide range of applications %J IEEE Journal of Solid-State Circuits %K ieee_jssc %V SC-19 %N 5 %D October 1984 %P 602-609 %A Amr Mohsen %A Roger U. Kung %A Carl J. Simonsen %A Joseph Schutz %A Paul D. Madland %A Esmat Z. Hamdy %A Mark T. Bohr %T The design and performance of CMOS 256K bit DRAM devices %J IEEE Journal of Solid-State Circuits %K ieee_jssc %V SC-19 %N 5 %D October 1984 %P 610-618 %A Hiroshi Kawamoto %A Takashi Shinoda %A Yasunori Yamaguchi %A Shinji Shimizu %A Kanji Ohishi %A Nobuyoshi Tanimura %A Tokumasa Yasui %T A 288K CMOS pseudostatc RAM %J IEEE Journal of Solid-State Circuits %K ieee_jssc %V SC-19 %N 5 %D October 1984 %P 619-627 %A Junzo Yamada %A Tsuneo Mano %A Jun'ichi Inoue %A Shigeru Nakajima %A Tadahito Matsuda %T A submicron 1 Mbit dynamic RAM with a 4-bit-at-a-time built-in ECC circuit %J IEEE Journal of Solid-State Circuits %K ieee_jssc %V SC-19 %N 5 %D October 1984 %P 627-633 %A Ryoichi Hori %A Kiyoo Itoh %A Jun Etoh %A Shojiro Asai %A Norikazu Hashimoto %A Kunihiro Yagi %A Hideo Sunami %T An experimental 1 Mbit DRAM based on high S/N design %J IEEE Journal of Solid-State Circuits %K ieee_jssc %V SC-19 %N 5 %D October 1984 %P 634-640 %A Roy E. Scheuerlein %A William W. Walker %A Donald G. Morency %A Wendell P. Noble %A Paul E. Bakeman,\ Jr. %A Dale L. Critchlow %T Shared word line DRAM cell %J IEEE Journal of Solid-State Circuits %K ieee_jssc %V SC-19 %N 5 %D October 1984 %P 640-645 %A Shishi Kanauchi %A Koichiro Okumura %A Shuichi Ohya %A Takeshi Watanabe %A Yoshihiro Shimamura %A Masanori Kikuchi %T A high performance 1 Mbit EPROM %J IEEE Journal of Solid-State Circuits %K ieee_jssc %V SC-19 %N 5 %D October 1984 %P 646-650 %A Fujio Masuoka %A Shoji Ariizumi %A Taira Iwase %A Michihiro Ono %A Norio Endo %T An 80ns 1 Mbit MASK ROM with a new memory cell %J IEEE Journal of Solid-State Circuits %K ieee_jssc %V SC-19 %N 5 %D October 1984 %P 651-657 %A Shigeru Tanaka %A Jun Iwamura %A Junichi Ohno %A Kenji Maeguchi %A Hiroyuki Tango %A Katsuyuki Doi %T A subnanosecond 8K-gate CMOS/SOS gate array %J IEEE Journal of Solid-State Circuits %K ieee_jssc %V SC-19 %N 5 %D October 1984 %P 657-663 %A William N. Johnson %A William V. Herrick %A William J. Grundman %T A VLSI VAX chip set %J IEEE Journal of Solid-State Circuits %K ieee_jssc %V SC-19 %N 5 %D October 1984 %P 663-674 %K MicroVAX %A Robert M. Supnik %T MicroVAX 32, a 32 bit microprocessor %J IEEE Journal of Solid-State Circuits %K ieee_jssc %V SC-19 %N 5 %D October 1984 %P 675-681 %A Robert W. Sherburne,\ Jr. %A Manolis G.H. Katevenis %A David A. Patterson %A Carlo H. Sequin %T A 32-bit NMOS microprocessor with a large register file %J IEEE Journal of Solid-State Circuits %K ieee_jssc %V SC-19 %N 5 %D October 1984 %P 682-689 %K RISC RISC-II %A Gil Wolrich %A Edward McLellan %A Larry Harada %A James Montanaro %A Robert A.J. Yodlowski %T A high performance floating point coprocessor %J IEEE Journal of Solid-State Circuits %K ieee_jssc %V SC-19 %N 5 %D October 1984 %P 690-696 %A Masaru Uya %A Katsuyuki Kaneko %A Juro Yasui %T A CMOS floating point multiplier %J IEEE Journal of Solid-State Circuits %K ieee_jssc %V SC-19 %N 5 %D October 1984 %P 697-702 %A Eral E. Swartzlander,\ Jr. %A Wendell K.W. Young %A Saul J. Joseph %T A radix 4 delay commutator for fast Fourier transform processor implementation %J IEEE Journal of Solid-State Circuits %K ieee_jssc %V SC-19 %N 5 %D October 1984 %P 702-709 %A Shoichi Shimizu %A Yukio Kamatani %A Nobuyuki Toyoda %A Katsue Kanazawa %A Masao Mochizuki %A Toshiyuki Terada %A Akimichi Hojo %T A 1 GHz 50 mW GaAs dual modulus divider IC %J IEEE Journal of Solid-State Circuits %K ieee_jssc %V SC-19 %N 5 %D October 1984 %P 710-715 %A Masahiro Hirayama %A Masayuki Ino %A Yutaka Matsuoka %A Masamitsu Suzuki %T A GaAs 4 kbit SRAM with direct coupled FET logic %J IEEE Journal of Solid-State Circuits %K ieee_jssc %V SC-19 %N 5 %D October 1984 %P 716-720 %A Yasuo Ikawa %A Nobuyuki Toyoda %A Masao Mochizuki %A Toshiyuki Terada %A Katsue Kanazawa %A Majomi Hiruse %A Takamaro Mizoguchi %A Akimichi Hojo %T A 1K-gate GaAs gate array %J IEEE Journal of Solid-State Circuits %K ieee_jssc %V SC-19 %N 5 %D October 1984 %P 721-728 %A Robert N. Deming %A Ricardo Zucca %A Richard P. Vahrenkamp %A L. Daniel Hou %A Barbara A. Naused %A Barry K. Gilbert %T A gallium arsenide configurable cell array using buffered FET logic %J IEEE Journal of Solid-State Circuits %K ieee_jssc %V SC-19 %N 5 %D October 1984 %P 728-738 %A Prabhakara C. Balla %A Andreas Antoniou %T Low power dissipation MOS ternary logic family %J IEEE Journal of Solid-State Circuits %K ieee_jssc %V SC-19 %N 5 %D October 1984 %P 739-749 %A Shuichi Fujita %A Yoshichika Ichimaya %A Akira Ishida %T Josephson dc-powered latch with the initial reset circuit %J IEEE Journal of Solid-State Circuits %K ieee_jssc %V SC-19 %N 5 %D October 1984 %P 750-754 %A Robert J. Bayruns %A R.L. Johnston %A Donald L. Fraser,\ Jr. %A San-Chin Fang %T Delay analysis of Si NMOS Gbit/s logic circuits %J IEEE Journal of Solid-State Circuits %K ieee_jssc %V SC-19 %N 5 %D October 1984 %P 755-764 %A Philip E. Fox %T An integrated approach to statistical modeling of bipolar devices for LSI %J IEEE Journal of Solid-State Circuits %K ieee_jssc %V SC-19 %N 5 %D October 1984 %P 765-772 %A Willy M.C. Samsen %A Peter M. van\ Peteghem %T An area-efficient approach to the design of very-large time constants in switched-capacitor integrators %J IEEE Journal of Solid-State Circuits %K ieee_jssc %V SC-19 %N 5 %D October 1984 %P 772-780 %A Charles M. Lee %A Hana Soukup %T An algorithm for CMOS timing and area optimization %J IEEE Journal of Solid-State Circuits %K ieee_jssc %V SC-19 %N 5 %D October 1984 %P 781-787 %A Masayuki Ishikawa %A Tadakatsu Kimura %A Norio Tamaki %T A CMOS adaptive line equalizer %J IEEE Journal of Solid-State Circuits %K ieee_jssc %V SC-19 %N 5 %D October 1984 %P 788-793 %A Allan L. Silburt %A A.R. Boothroyd %A Mohamed I. Elmasry %T A novel multiple threshold MOSFET structure for A/D and D/A conversion %J IEEE Journal of Solid-State Circuits %K ieee_jssc %V SC-19 %N 5 %D October 1984 %P 794-802 %A Kotaro Kato %A Terukazu Ono %A Yoshihito Ameniya %T A monolithic 14 bit D/A converter fabricated with a new trimming technique (DOT) %J IEEE Journal of Solid-State Circuits %K ieee_jssc %V SC-19 %N 5 %D October 1984 %P 802-807 %A Hu H. Chao %A Shauchi Ong %A Mon Yen Tsai %A Feng-Hsien W. Shih %A John C. Hou %A Kelvin W. Lewis %A Jeffrey Y.-F. Tang %A Cynthia A. Trempel %A Richard W. Hadsell %A Hwa Nien Yu %A Paul F. Greiger %A Robert L. Franch %A Peter E. McCormick %A Clinton V. Davis,\ Jr. %A Andrew L. Diamond %A Thomas J. Medve %T Micro/370: a 32-bit single-chip microprocessor %J IEEE Journal of Solid-State Circuits %K ieee_jssc %V SC-21 %N 5 %D October 1986 %P 733-740 %A Joan M. Pendleton %A Shing I. Kong %A Emil W. Brown %A Frank Dunlap %A Christopher Marino %A David M. Ungar %A David A. Patterson %A David A. Hodges %T A 32-bit microprocessor for Smalltalk %J IEEE Journal of Solid-State Circuits %K ieee_jssc %V SC-21 %N 5 %D October 1986 %P 741-749